Commit Graph

27854 Commits

Author SHA1 Message Date
Wei6 Xu ff306cfd6c FmpDevicePkg/Test: Add FmpDependencyLib unit test
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2696

* Add unit tests for EvaluateDependency API in FmpDependencyLib.
* Add Test/FmpDeviceHostPkgTest.dsc to build host based unit test.
* Update FmpDevicePkg.dsc to build target based unit test.
* Update FmpDevicePkg.ci.yaml to build and run host based test.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2020-05-15 06:11:44 +00:00
Wei6 Xu a93bf06b1d FmpDevicePkg: Add FmpDependency library class and BASE instance
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2696

This library provides services to evaluate Fmp capsule dependency
expression, validate dependency expression and get dependency
from firmware image.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2020-05-15 06:11:44 +00:00
Oleksiy Yakovlev 154e243a99 MdePkg: UEFI JSON Capsule Support
Added Guids and structures, that defines the work flow to perform
capsule update using JSON objects.
(UEFI 2.8 mantis 1935)

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Oleksiy Yakovlev 2552fd58f5 MdePkg: Add UEFI Spec Revision 2.8
Added entrie in the EFI_SYSTEM_TABLE related definitions section,
to signify UEFI 2.8 spec revision.
(UEFI 2.8 mantis 1926)

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Oleksiy Yakovlev f8edb7e998 MdePkg: Bootable NVDIMM namespaces
Provided a mechanism for UEFI FW to identify and hand off bootable
NVDIMM namespaces to the OS by standardizing the EFI device path.
EFI device path for physical NVDIMM devices changed from an ACPI
_ADR device to an ACPI NVDIMM device for correctness.
(UEFI 2.8 mantis 1858)

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Oleksiy Yakovlev 5c7526f501 BaseTools: Bootable NVDIMM namespaces
Provided a mechanism for UEFI FW to identify and hand off bootable
NVDIMM namespaces to the OS by standardizing the EFI device path.
EFI device path for physical NVDIMM devices changed from an ACPI
_ADR device to an ACPI NVDIMM device for correctness.
(UEFI 2.8 mantis 1858)

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Oleksiy Yakovlev 8adad18a94 MdePkg: REST style formset
New ClassGuid EFI_HII_REST_STYLE_FORMSET_GUID is defined.
In question level, a new flag EFI_IFR_FLAG_REST_STYLE is defined.
(UEFI 2.8 mantis 1853)

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Oleksiy Yakovlev ebe377f9eb BaseTools: REST style formset
In question level, a new flag EFI_IFR_FLAG_REST_STYLE is defined.

(UEFI 2.8 mantis 1853)

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Oleksiy Yakovlev 7e9cef643d MdePkg: Extend SERIAL_IO with DeviceTypeGuid
EFI_SERIAL_IO_PROTOCOL_REVISION incremented to 0x00010001.
CONST EFI_GUID *DeviceTypeGuid field added to the protocol structure.
UEFI 2.8 mantis 1832.

Signed-off-by: Oleksiy Yakovlev <oleksiyy@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
2020-05-15 05:05:52 +00:00
Roman Bolshakov bcf181a33b OvmfPkg: Skip initrd command on Xcode toolchain
OVMF booting stops with the assert if built with Xcode on macOS:

  Loading driver at 0x0001FAB8000 EntryPoint=0x0001FABF249 LinuxInitrdDynamicShellCommand.efi
  InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 1F218398
  ProtectUefiImageCommon - 0x1F218140
    - 0x000000001FAB8000 - 0x0000000000008A60

  ASSERT_EFI_ERROR (Status = Unsupported)
  ASSERT LinuxInitrdDynamicShellCommand.c(378): !EFI_ERROR (Status)

The assert comes from InitializeHiiPackage() after an attempt to
retrieve HII package list from ImageHandle.

Xcode still doesn't support HII resource section and
LinuxInitrdDynamicShellCommand depends on it. Likewise 277a3958d9
("OvmfPkg: Don't include TftpDynamicCommand in XCODE5 tool chain"),
disable initrd command if built with Xcode toolchain

Fixes: ec41733cfd ("OvmfPkg: add the 'initrd' dynamic shell command")
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Message-Id: <20200514134820.62047-1-r.bolshakov@yadro.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2020-05-14 17:11:07 +00:00
Shenglei Zhang 8b680e4af1 MdeModulePkg/RegularExpressionDxe: Optimize the code infrastructure
OnigurumaIntrinsics.c is now not used. So the implement of function
'memcpy' is now not., which causes build failure with CLANG9 and
XCODE. I remove OnigurumaIntrinsics.c and move the necessary function
implement to OnigurumaUefiPort.c/h.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2020-05-14 14:38:54 +00:00
Chasel Chiu f2cdb268ef IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698

To enhance FSP silicon initialization flexibility an optional
Multi-Phase API is introduced and FSP header needs update for
new API offset. Also new SecCore module created for
FspMultiPhaseSiInit API

New ARCH_UPD introduced for enhancing FSP debug message
flexibility now bootloader can pass its own debug handler
function pointer and FSP will call the function to handle
debug message.
To support calling bootloader functions, a FspGlobalData field
added to indicate if FSP needs to switch stack when FSP running
on separate stack from bootloader.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
2020-05-14 12:34:01 +00:00
Feng, YunhuaX ceacd9e992 BaseTools: Fix parse PCD GUID expression issue
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2686

The build tool will give an incorrect GUID value if the GUID includes character ' or " ASCII value.
This patch is going to fix this issue.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Yunhua Feng <yunhuax.feng@intel.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2020-05-13 06:37:18 +00:00
Michael Kubacki 242ab73d7f BaseTools/Ecc: Replace deprecated function time.clock()
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2707

Ecc fails with Python 3.8 because it uses the deprecated time.clock()
function - https://docs.python.org/3.7/library/time.html#time.clock

This change updates EccMain.py to use time.perf_counter().

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2020-05-13 05:52:03 +00:00
Ard Biesheuvel 88899a372c StandaloneMmPkg: switch to MM communicate 2 protocol
Update the reference to MM communicate to refer to the MM communicate 2
protocol instead. This makes no difference for the MM side of the
implementation, but is more accurate nonetheless, since the original MM
protocol does not work in combination with standalone MM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Ard Biesheuvel be4e0cfbad MdeModulePkg/VariableSmmRuntimeDxe: switch to MM communicate 2
Switch to the new MM communicate 2 protocol which supports both
traditional and standalone MM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Ard Biesheuvel fa37a846d0 MdeModulePkg/FaultTolerantWriteSmmDxe: switch to MM communicate 2
Switch to the new MM communicate 2 protocol which supports both
traditional and standalone MM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Ard Biesheuvel 789ea79e94 MdeModulePkg/VariableInfo: switch to MM communicate 2 protocol
Switch to the new MM communicate 2 protocol which supports both
traditional and standalone MM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Ard Biesheuvel 3e3acb3a27 ArmPkg/MmCommunicationDxe: expose MM Communicate 2 protocol
Implement the new MmCommunication2 protocol which supports the use
of standalone MM at runtime inside an address space that has been
virtually remapped by the OS.

Note that the implementation of the old MM Communicate protocol is
removed: it never worked correctly so there is no point in keeping it.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Ard Biesheuvel 9ad2b981bd MdeModulePkg/SmmIpl: expose MM communicate 2 protocol
The MM communicate 2 protocol was introduced to factor out the mismatch
between traditional MM, which requires the physical address of the MM
buffer to be passed, and standalone MM, which copies the MM communicate
buffer data into a separate buffer, requiring the virtual address. For
this reason, MM communicate 2 carries both addresses, allowing the
implementation to decide which address it needs.

This hides this implementation detail from the callers of the protocol,
which simply passes both addresses without having to reason about what the
implementation of the protocol actually needs.

Note that the old version of the protocol is retained, in order to support
existing implementations that don't require this flexibility.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Ard Biesheuvel c857042471 MdePkg: introduce MM communicate 2 protocol
Add the protocol definition of the MM communicate 2 protocol,
which has been introduced by version 1.7 errata A of the PI spec.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
2020-05-12 19:23:44 +00:00
Lendacky, Thomas 9378310dd8 UefiCpuPkg/CpuExceptionHandler: Revert CpuExceptionHandler binary patching
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2340

Now that an XCODE5 specific CpuExceptionHandlerLib library is in place,
revert the changes made to the ExceptionHandlerAsm.nasm in commit
2db0ccc2d7 ("UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool
chain") so that binary patching of flash code is not performed.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Liming Gao <liming.gao@intel.com>
Acked-by: Bret Barkelew <bret.barkelew@microsoft.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <810f67d8604c054c09d17a22f0bcfaeb41ee8e3b.1588856809.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2020-05-11 19:25:33 +00:00
Lendacky, Thomas b304d2807b OvmfPkg: Use toolchain appropriate CpuExceptionHandlerLib
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2340

During the SEC phase, use the XCODE5 CpuExceptionHandlerLib library in
place of the standard library when building with the XCODE5 toolchain.
The SEC XCODE5 version of the library performs binary patching and should
only be used when building with the XCODE5 toolchain.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Anthony Perard <anthony.perard@citrix.com>
Cc: Julien Grall <julien@xen.org>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <0cfdd51deb6d39e08380645f2022b9b76e29f66f.1588856809.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2020-05-11 19:25:33 +00:00
Lendacky, Thomas ec94e97a6e UefiCpuPkg/CpuExceptionHandler: Make XCODE5 changes toolchain specific
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2340

Commit 2db0ccc2d7 ("UefiCpuPkg: Update CpuExceptionHandlerLib pass
XCODE5 tool chain") introduced binary patching into the exception handling
support. CPU exception handling is allowed during SEC and this results in
binary patching of flash, which should not be done.

Separate the changes from commit 2db0ccc2d7 into an XCODE5 toolchain
specific file, Xcode5ExceptionHandlerAsm.nasm, and create a new SEC INF
file for the XCODE5 version of CpuExceptionHandlerLib.

Since binary patching is allowed when running outside of flash, switch
the Dxe, Pei and Smm versions of the CpuExceptionHandlerLib over to use
the Xcode5ExceptionHandlerAsm.nasm file to retain current functionality.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <9075570487616c731033a5738f6a444a15d71b74.1588856809.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2020-05-11 19:25:33 +00:00
Sean Brogan c8543b8d83 BaseTools/Plugin: Update HostBasedUnitTestRunner to support Linux
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2513

Update HostBasedUnitTestRunner plugin to support the Linux environment
and remove any Windows only logic.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2020-05-08 05:54:46 +00:00
Sean Brogan f4f9c4cb63 .pytool/CISettings: Remove Windows only scope for host based unit tests
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2513

Remove Windows only scopes in the CISettngs file

Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2020-05-08 05:54:46 +00:00
Leif Lindholm f355b98606 BaseTools: add handling for 'S:' flag to GetMaintainer.py
GetMaintainer.py already extracts the value of any S: tags for sections,
but it doesn't do anything with that information.

Print a warning message, with the status, for each matching section with
a status explicitly set to anything other than 'Supported' or
'Maintained'.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
2020-05-08 04:37:08 +00:00
Rebecca Cran 3a3713e62c BaseTools: add repo name option to SetupGit.py
Allow users who didn't clone one of the TianoCore repos from a
canonical URL to specify the name of the repo (edk2, edk2-platforms
or edk2-non-osi) when running SetupGit.py to allow them to configure
their repo properly.

The new option is:

  -n repo, --name repo  set the repo name to configure for, if not
                        detected automatically

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Bob Feng <bob.c.feng@intel.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2020-05-08 03:59:29 +00:00
Abner Chang 8293e6766a NetworkPkg: Add RISCV64 architecture
Add RISCV64 Arch in NetworkPkg.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Acked-by: Siyuan Fu <siyuan.fu@intel.com>

Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 86c4f437d8 MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
Implementation of RISC-V DxeIPL.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Co-authored-by: Daniel Helmut <daniel.schaefer@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>

Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 00acc6cbf9 MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 architecture
Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Hao A Wu <hao.a.wu@intel.com>

Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang fd8c6bed8a MdeModulePkg/Logo:Add RISCV64 architecture
Add RISCV64 Arch.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Zhichao Gao <zhichao.gao@intel.com>

Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 4e74764245 MdePkg/BaseSafeIntLib: Add RISCV64 arch for BaseSafeIntLib.
Add RISCV64 arch for BaseSafeIntLib library.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 8c43227c64 MdePkg/BaseSynchronizationLib: RISC-V cache related code.
Support RISC-V cache related functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 3fd8800954 MdePkg/BaseCpuLib: RISC-V Base CPU library
implementation.

Implement RISC-V CPU related functions in BaseCpuLib.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 54a3d5ec48 MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
Support RISC-V image relocation.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 089e9c19a8 MdePkg/BaseIoLibIntrinsic: Rename IoLibArm.c=>IoLibNoIo.c
RISC-V MMIO library instance.
IoLibArm.c in fact implements a generic Mmio-only (and ANSI
C compliant), so rename it to better reflect this.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 38e72aa877 MdePkg/BaseCacheMaintenanceLib:
RISC-V cache maintenance implementation.

Implement RISC-V cache maintenance functions in
BaseCacheMaintenanceLib.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 7601b251fd MdePkg/BaseLib: BaseLib for RISCV64 architecture
Add RISC-V RV64 BaseLib functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang d3abb40d77 MdePkg/Include: RISC-V definitions.
Add RISC-V processor related definitions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 1510d6a391 MdePkg: Add RISC-V RISCV64 binding
Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang e6956d0052 .pytool: Add RISC-V architecture on RISC-V EDK2 CI.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562

Add RISC-V architecture on RISC-V EDK2 CI testing.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>

Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang 722da9078e .azurepipelines: Add RISC-V architecture on RISC-V EDK2 CI.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562

Add RISC-V architecture on RISC-V EDK2 CI.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>

Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
2020-05-07 03:17:15 +00:00
Abner Chang ea56fa3d47 BaseTools: Enable RISC-V architecture for RISC-V EDK2 CI.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562

EDK CI for RISC-V architecture

Enable RISC-V architecture for RISC-V EDK2 CI testing.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>

Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
2020-05-07 03:17:15 +00:00
Krzysztof Koch faef5a367c ShellPkg: acpiview: Check if SBBR mandatory ACPI tables are installed
For Arm-based platforms, count the instances of installed tables for
each ACPI table listed as 'mandatory' in any Server Base Boot
Requirements (SBBR) specification.

Validate that the all the mandatory SBBR tables present. Report an error
for each missing table.

This new feature is optional and can be enabled with the -r command line
parameter.

Reference(s):
    - Arm Server Base Boot Requirements 1.2, September 2019
    - Arm Server Base Boot Requirements 1.1, May 2018
    - Arm Server Base Boot Requirements 1.0, March 2016

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2020-05-06 17:00:57 +00:00
Krzysztof Koch f793bfcae9 ShellPkg: acpiview: Add library for SBBR ACPI requirements validation
For Arm-based platforms, define and implement an interface for Server
Base Boot Requirements (SBBR) compliance checks. The library is
responsible for validating that all mandatory ACPI tables are installed
on the platform.

Internally, the library maintains a data structure which tracks
instance counts for ACPI tables which are labeled as 'mandatory' in any
SBBR specification version. The provided interface allows:
- resetting all instance counts to 0
- incremementing the instance count for a table with a given signature
- validating the instance counts against the requirements in SBBR

The ACPI table requirements for each SBBR spec version are represented
internally as a list of table signatures.

Every missing mandatory table (for the input SBBR version) is reported
to the user as a separate error. If all requirements are met, an info
message is displayed.

Reference(s):
    - Arm Server Base Boot Requirements 1.2, September 2019
    - Arm Server Base Boot Requirements 1.1, May 2018
    - Arm Server Base Boot Requirements 1.0, March 2016

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2020-05-06 17:00:57 +00:00
Krzysztof Koch 8af507c1f1 ShellPkg: acpiview: Add -r parameter for table requirements validation
Define a new command line parameter '-r' to enable checking if all
mandatory ACPI tables listed in a specification are present.

The -r parameter takes an integer value to specify which specification
the validation should be performed against.

The parameter is used to set two Acpiview variables. An interface to
access these variables is implemented in this patch.

The new functionality is aimed at Arm-based platforms, however,
there are no restriction on extending it to other architectures.
For the 32-bit and 64-bit Arm architectures, the possible values for
the -r parameter are:
  0: Arm Server Base Boot Requirements 1.0, March 2016
  1: Arm Server Base Boot Requirements 1.1, May 2018
  2: Arm Server Base Boot Requirements 1.2, September 2019

Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
2020-05-06 17:00:57 +00:00
Ard Biesheuvel befd18fca6 EmbeddedPkg/EmbeddedPkg.dsc: remove some stale component references
Some driver were recently moved to edk2-platforms, but the DSC file
in EmbeddedPkg still refers to them. Drop these references.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
2020-05-06 10:21:31 +00:00
Guomin Jiang 469eb46169 CryptoPkg/Pkcs7: Extend support for other OID types
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2539

Microsoft signtool supports creation of attached P7's with any OID payload
via the "/p7co" parameter. It is necessary to check the data before get
the string.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyux.lu@intel.com>
Signed-off-by: Guomin Jiang <guomin.jiang@intel.com>

Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
2020-05-06 03:37:39 +00:00
Kun Qin 55d6e39f72 FmpDevicePkg/FmpDxe: Fix uninitialized pointer dereference
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2602

Zero the allocated buffer in case GetImageInfo `continue` in the middle of
a loop. This will cause unexpected GetImageInfo failure not clearing the
corresponding entry and lead to GP faults when dereferencing this entry.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
Reviewed-by: Guomin Jiang <guomin.jiang@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2020-05-06 03:04:17 +00:00