Remove EdkShellBinPkg in CorebootPayloadPkg.fdf.
https://bugzilla.tianocore.org/show_bug.cgi?id=1108
v3:Remove FULL_BIN and change SHELL_TYPE from FULL_BIN
to UEFI_BIN.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Change-Id: I4db7068a3a1f68a1f6303079b73dc548c9feb2e3
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Removing rules for Ipf sources file:
* Remove the source file which path with "ipf" and also listed in
[Sources.IPF] section of INF file.
* Remove the source file which listed in [Components.IPF] section
of DSC file and not listed in any other [Components] section.
* Remove the embedded Ipf code for MDE_CPU_IPF.
Removing rules for Inf file:
* Remove IPF from VALID_ARCHITECTURES comments.
* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
* Remove the INF which only listed in [Components.IPF] section in DSC.
* Remove statements from [BuildOptions] that provide IPF specific flags.
* Remove any IPF sepcific sections.
Removing rules for Dec file:
* Remove [Includes.IPF] section from Dec.
Removing rules for Dsc file:
* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
* Remove any IPF specific sections.
* Remove statements from [BuildOptions] that provide IPF specific flags.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chen A Chen <chen.a.chen@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Ma, Maurice <maurice.ma@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
To fix building with SOURCE_DEBUG_ENABLE, add DebugAgentLib for
LibraryClasses.common.DXE_DRIVER, as is done with Vlv2TbltDevicePkg.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Alex James <theracermaster@gmail.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Use ZeroMem() to initialize (or re-initialize) all fields in temporary
PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
helpful for future extension: when we add new fields to
PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
safely be zero, this code will not suffer from an additional change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
According to UEFI Spec, EFI_GRAPHICS_OUTPUT_PROTOCOL.Mode->Info->
PixelsPerScanLine may contain padding pixel elements outside the area
covered by HorizontalResolution for performance reasons or due to hardware
restrictions. CorebootPayloadPkg's FbGop driver doesn't follow this
requirement, and produces PixelsPerScanLine simply as
HorizontalResolution. This needs to be fixed to reflect the real length
of a framebuffer scanline.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Benjamin You <benjamin.you@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Fetch BytesPerScanLine from coreboot table to reflect how the actual
framebuffer is set up instead of guessing it from the horizontal
resolution.
This fixes a garbled display when HorizontalResolution * (BitsPerPixel
/ 8) and pFbInfo->BytesPerScanLine don't match.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=642
Add top level License.txt file with the BSD 2-Clause
License that is used by the majority of the EKD II open
source project content. Merge copyright statements
from the BSD 2-Clause License files in each package
directory and remove the duplication License.txt
file from package directories.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
https://bugzilla.tianocore.org/show_bug.cgi?id=629
Move Contributions.txt that contains the TianoCore
Contribution Agreement 1.0 to the root of the edk2
repository and remove the duplicate Contributions.txt
files from all packages.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Use EfiEventGroupSignal from UefiLib and remove
InternalBdsEmptyCallbackFuntion.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=298
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Add APRIORI file to allow status code related DXE drivers to
be dispatched earlier so that debug message can also be seen
much earlier. With this, lots of DXE driver debug message will
be missing.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Current CorebootPayloadPkgIa32X64.dsc contains "-flto" flag to
request GCC link time optimization. However, this feature is
only supported by newer GCC compiler, and it will break the
debug build with GCC4.8. To fix it, the extra compiling flags
are removed. It allows the default build flags set by the EDKII
build environment to be used.
With this fix, CorebootPayloadPkg 64bit debug build can pass
using GCC 4.8.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
On old platform without PCIe express support, the PciLib needs to
be mapped to PciLibCf8 instance to make it work. On new platform
with PCIe express support, the PciLib needs to be mapped to
PciLibPciExpress to allow access to extended PCIe configuration
space. This patch allows to select the PciLib instance between
PciLibCf8 and PciLibPciExpress using the PCIE_BASE macro through
build command line.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Sunny Wang <sunnywang@hpe.com>
The previous change to disable deprecated APIs in CorebootPayloadPkg
used "/D" instead of "-D". It caused Linux GCC build error. Correct
it to use "-D" instead.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Rusty Coleman <rcoleman@sigovs.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed-by: Rusty Coleman <rcoleman@sigovs.com>
- dirver -> driver
- futhure -> future
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Also add Down key to Boot Manager Menu since some serial
terminals don't support F2 key.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
To let it boot to OS automatically, make built in shell
as the last boot option.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
The current CorebootPayloadPkg will use the legacy 8254 timer
driver as the default. However, on some platforms legacy timer
might not exist anymore. This patch adds HPET timer driver as
a build option.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>
Update PlatformBootManagerLib to notify EndOfDxe event and install
SmmReadyToLock protocol since other modules depend on them.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: gdong1 <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Update CbSupportPei to consume the new library, so platform could provide
platform specific library instance to parse platform specif info.
And add a NULL library instance to pass build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: gdong1 <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated. As a result replaced PcdSet32
with PcdSet32S accordingly to make the build pass.
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
Cc: Prince Agyeman <prince.agyeman@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=163
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
The current CorebootPayloadPkg will print the following message
"InsertImageRecord - Section Alignment(0x20) is not 4K" during
boot. It is caused by the section alignment arranged by the linker.
This patch change the alignment to 4K for runtime drivers.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
The current CorebootPayloadPkg uses PEI/DXE StatusCode drivers from
IntelFrameworkModulePkg. This patch switches to use the StatusCode
driver from MdeModulePkg instead.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
The current PCI resource limit calculation in CorebootPayloadPkg
PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge
driver's expectation.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Section alignment of .data in GCC49 and GCC5 are 0x40
rather than 0x20 in GCC48 and below.
This causes a hang in PeiCore.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
MpInitLib is consumed by CpuDxe
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation. Instead, the lowest non-zero bit should be used for BAR
size calculation.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
When coreboot uses different baud rate from the default (115200), the
current BDS driver will not be able to enable serial console display
due to the inconsistent serial port PCD settings. By adding the
PlatformHookLib reference in the inf file, it will enforce the PCDs
to be aligned with what have been passed from coreboot.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Lee Leahy <leroy.p.leahy@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed by: Lee Leahy <leroy.p.leahy@intel.com>
Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and
PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will
switch to use the standard PciBusDxe and PciHostBridgeDxe from
MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib
is added to collect pre-allocated PCI resources.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Fix Linux build failure with GCC 4.8.4 due to missing braces.
Change-Id: Ic0de6520605149f1bb74f8b60ce8cab8beda10a4
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Since the new BdsDxe driver in MdeModulePkg is used, the old
BdsPlatform library is not used any more and should be removed.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Switch over to use BdxDxe generic driver in MdeModulePkg.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
In order to use the generic BdsDxe in MdeModulePkg, a platform
specific PlatfromBootManagerLib is required. This library will
help update the ConIn, ConOut and ErrOut variables.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Use generic SerialDxe driver in MdeModulePkg instead of the one
in CorebootModulePkg. By doing this the reference for
PciSioSerialDxe driver will also be removed from DSC and FDF file.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Add the USB OHCI driver from revision 24ca2f35 of QuarkSocPkg.
Change-Id: Ie7aa0bc47d4ff06adc57976a5efb0e40ce4e1673
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Add SD and eMMC DXE driver support to CorebootPayloadPkg.
Change-Id: Ibfd3a2cc32a653ce51e38d9157ea3c6da25a5474
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Set the proper Shell file GUID so that the BDS transfers control to the
Shell.
Change-Id: I816636a340bbe2f76ac1973b9cb685084c4f88a0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Use the BaseSerialPortLib16550 which sets RTS and DTR during
initialization. This fixes the mis-matched flow control issue when
the flow control signals are connected between the host and target
and the host has flow control enabled.
Change-Id: I3505e129b2de3c5c17fff23c62553f15cd892dca
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Set the vendor to 0xffff which indicates the end of the list.
Change-Id: If6475e04d3675f0a932571a85d1dd3f301416b6a
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
eviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Convert to using DOS line endings.
Change-Id: Ie2f148867d9b2b386d556583afb6716ec21399e9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Pass the serial port baudrate, register stride, input clock rate and
ID from coreboot to CorebootPayloadPkg.
Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Use the serial drivers which update the serial PCDs from
PlatformHookLib.
Change-Id: Ie6a3526d56332ee1cf07edb24ff39634a981183f
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Add a define and use it with MaxLogicalProcessorNumber to enable this
PCD to be changed via the command line. Quark needs to set this value
to one during the builds.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Allow the serial port configuration to be overriden from the command
line.
Make the debug serial PCDs patchable in module.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Add all of the shell options from ShellBinPkg including building the
shell from source.
Enable link time optimization for GCC debug builds to keep the size
under 0x3e0000.
Test: Use -DSHELL_TYPE=BUILD_SHELL command line options to build the
shell from source. Run the result on Galileo Gen2.
Change-Id: I1e12adb57960ac5e75e682073540a9322aa03081
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Remove the references to DuetPkg. Copy the files from revision
ffea0a2ce2 of DuetPkg into
CorebootModulePkg. The components include:
* PciBusNoEnumerationDxe
* PciRootBridgeNoEnumerationDxe
* SataControllerDxe
TEST=Build and run on Galileo Gen2
Change-Id: Id07185f7e226749e5f7c6b6cb427bcef7eac8496
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
shenglei
Wonkyu Kim
chenc2
Ruiyu Ni
Alex James
Heyi Guo
Benjamin You
Arthur Heymans
Michael D Kinney
Star Zeng
Maurice Ma
gdong1
Prince Agyeman
Leahy, Leroy P