Commit Graph

4 Commits

Author SHA1 Message Date
Antoine Coeur 06516768ed CorebootModulePkg: Fix various typos
Fix various typos in CorebootModulePkg.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Coeur <coeur@gmx.fr>
Reviewed-by: Benjamin You <benjamin.you@intel.com>
2019-02-12 10:48:39 +08:00
Leahy, Leroy P bb0831670f CorebootModulePkg/BaseSerialPortLib: Set DTR and RTS
Ensure communication between the host and the UEFI system running
CorebootPayloadPkg.  In cases where the host has flow control enabled
and the serial connection is providing the flow control signals, the
host will not be able to send data to the UEFI system because DTR and
RTS are not present.  The host may also discard all output data from
the UEFI system because DTR is not present.  By setting DTR and RTS
in the UART initialization code this case works properly.

Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
2016-05-10 10:12:15 -07:00
Leahy, Leroy P b08993bd13 CorebootModulePkg/BaseSerialPortLib16550: Remove white-space
Remove trailing white space.

Change-Id: I73c3a3e1e55eec20b09443de1966573c97fa74f8
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
2016-05-10 10:11:49 -07:00
Leahy, Leroy P 12460e227f CorebootModulePkg: Add BaseSerialPortLib16550
Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision
89ecd4cf80.

Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
2016-05-10 10:10:19 -07:00