Commit Graph

8 Commits

Author SHA1 Message Date
Olivier Martin c4149528d4 ArmPkg/CpuDxe: Fixed AArch64 MMU
When the function that determines the size of a contiguous region
was returning from a sub-level table scanning it was forgetting to
move to the next entry of its own level table.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17832 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-06 16:53:37 +00:00
Olivier Martin 48ef4e4276 ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level
If the first entry of the memory map is in the third level (case when the region
at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3
(=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3).
The first condition in GetFirstPageAttribute() needed the table level
to not mix these two descriptor types.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14 05:32:07 +00:00
Olivier Martin 0127372430 ArmPkg/CpuDxe: Fixed confusion in AArch64 Table descriptor types
Table Descriptor and Level-3 Block entry descriptors have the same
translation table type value (ie: 0x3).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-14 16:32:38 +00:00
Olivier Martin 429358b59d ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()
The wrong attribute was used to set the region.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16 09:32:59 +00:00
Olivier Martin 2e969d2e9e ArmPkg/CpuDxe: Added support to not set a memory region with the same attribute
Changing the attribute implies some cache management (clean & invalidate).
Preventing the cache management should improve the performance.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19 17:38:39 +00:00
Olivier Martin 047c0cbb1e ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronization
- Fix the length used to set the GCD Memory Space attribute
- Print a warning message if the given length of a memory space region is not 4KB-aligned

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19 17:33:31 +00:00
Olivier Martin 5b53eaffe8 ArmPkg,ArmPlatformPkg: Free memory allocated by Get.*SpaceMap()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14507 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26 17:12:12 +00:00
Harry Liebel 25402f5d06 ArmPkg: Added Aarch64 support
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18 18:07:46 +00:00