Commit Graph

16667 Commits

Author SHA1 Message Date
Ard Biesheuvel a7ab160209 BaseTools AARCH64: remove incremental linker script for 64K alignment
Now that we moved all users to the unified GCC linker script, remove
the old 64 KB incremental linker script for AARCH64 since it is now
unused.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18141 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:23:36 +00:00
Ard Biesheuvel 5670dd5e99 ArmVirtPkg: move to unified GCC linker script
Move to the parametrised generic GCC linker script and set 64 KB
alignment, instead of using the AARCH64 specific incremental linker
script for 64 KB alignment which is about to be removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18140 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:23:26 +00:00
Ard Biesheuvel b0fd0556fc ArmPlatformPkg/ArmVExpressPkg: move to unified GCC linker script
Move to the parametrised generic GCC linker script and set 64 KB
alignment, instead of using the AARCH64 specific incremental linker
script for 64 KB alignment which is about to be removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18139 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:23:16 +00:00
Ard Biesheuvel 6b3720e438 BaseTools AARCH64: move to unified GCC linker script
Drop the GCC AARCH64 specific linker script and use the new
unified one instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18138 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:23:05 +00:00
Ard Biesheuvel 233bd25b00 BaseTools GCC: move AutoGen.obj contents to .text section
All AutoGen.obj files consist of global GUID definitions, fixed
and patchable PCDs and other data that is essentially read-only at
runtime but has not been declared as such for various reasons.

By moving these contents to .text we achieve two things:
- global GUIDs and other data items which must be constant for correct
  program operation can no longer be modified, for instance, when
  running a DXE_RUNTIME_MODULE binary under the OS with the Properties
  Table feature for memory protection enabled;
- the .data section becomes smaller, and may be dropped completely for
  many XIP modules, which reduces wasted FV space if the PE/COFF section
  alignment is large.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18137 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:22:50 +00:00
Ard Biesheuvel 56948ba190 BaseTools GCC: align start of .data to .text alignment
Now that GenFw honors the ELF section alignment when placing the
PE/COFF sections in the output, the start of the PE/COFF version of
.data will be aligned to the alignment of .text if its alignment is
higher than the default. So duplicate this behavior in the ELF output,
this will make the memory layout of the PE/COFF binary match the
layout of the ELF version more closely.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18136 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:22:39 +00:00
Ard Biesheuvel efe690cab3 BaseTools GCC: add unified GCC linker script for all archs and versions
This unifies all GCC linker scripts into a single parametrised GCC
linker script that can be used for all GCC versions and architectures.

The two parameters that can be set on the linker command line are:
- PECOFF_HEADER_SIZE, this is a build time property of GenFw, but
  its value is different between 32-bit and 64-bit;
- common-page-size, this can be set using -z on the ld command line,
  and controls the value of the COMMONPAGESIZE constant when used in
  a linker script. This value is used for the minimum section alignment.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18135 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:22:28 +00:00
Ard Biesheuvel c28a4ab663 BaseTools IA32/X64: get header size and alignment from ld commandline
Instead of hardcoding the values for the PE/COFF header size and the
section alignment, set them on the linker command line. This factors
out these values from the various linker scripts, which will allow us
to unify them in a subsequent patch.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18134 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:22:16 +00:00
Ard Biesheuvel 25e63063e3 BaseTools IA32/X64: move .got contents to the PE/COFF .text section
Move the .got contents to the PE/COFF .text section. This should be
a no-op, since we typically don't generate position independent code
(i.e., using -fPIC). But since the GOT contains variable addresses that
are updated at relocation time only, its contents are best kept in .text
to prevent them from being overwritten inadvertently.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18133 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:22:00 +00:00
Ard Biesheuvel cdeb268cb0 BaseTools IA32/X64: drop redundant alignment from linker script
There is no need to pad out the end of a section of the start of
the following section is aligned to the same value. So drop the
redundant ALIGN() statements.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18132 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:21:49 +00:00
Ard Biesheuvel fa1d29d5cc BaseTools IA32/X64: move .rodata to PE/COFF .text section
The .rodata ELF section contains constant non-executable data that
should never be modified by the program itself. Since the risk of
inadvertent modification is typically higher than the risk of
inadvertent execution, it makes sense to put this data in the
R-X .text section rather than in the RW- .data section.
So move it there.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18131 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:21:39 +00:00
Ard Biesheuvel e90ba6e1ea BaseTools IA32/X64: remove NOP padding from X86/IA32 GCC linker scripts
The NOP padding in the GCC linker scripts ensures that all empty
regions in the ELF binary are filled with x86 NOP instructions.

There is no upside to doing this: if the CPU ends up executing these
instructions, we have little hope of resuming normal execution of the
program anyway. And having NOP slides in memory only makes it easier
for attackers to launch exploits. So remove them.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18130 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 08:21:28 +00:00
Qiu Shumin 37ee497e78 SecurityPkg/Tcg/MemoryOverwriteRequestControlLock: Add missing header file description in INF file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Yao Jiewen <Jiewen.Yao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18129 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 07:14:11 +00:00
Eric Dong e2f0fffd12 Nt32Pkg: Remove old useless bds platform lib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18128 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 05:31:41 +00:00
Eric Dong 99eda88580 Nt32Pkg: Do connect all and Refresh boot option action after console is connected.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18127 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 05:30:25 +00:00
Eric Dong 3af6a17f64 Fixed GCC49 build fail issue.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18126 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 03:22:49 +00:00
Liming Gao 3d44658ca8 MdeModulePkg PeiCore: Add PCD to specify PEIM Shadow
v2 changelog:
Check CurrentPeimHandle to check the matched PeimHandle.
Add check point to ShadowPeiCore based on PCD.

v1 changelog:
PeiCore LoadImage always shadow itself and PEIM on normal boot after
the physical memory is installed. On the emulator platform, the shadow
may be not necessary. To support such usage, new PCD PcdShadowPeimOnBoot
is introduced to specify whether loads PEIM in memory by default.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18125 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 03:18:37 +00:00
Qiu Shumin 496b0dd00c IntelFspPkg: Remove the const condition if statement to refine the code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.yao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18124 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-03 02:59:55 +00:00
Yao, Jiewen b23441875c Add Dual-FSP support (MemoryInitUpd/SiliconInitUpd)
Add FspUpdSignatureCheck() API in FspSecPlatformLib, so that FspSecCore can check if UPD data is valid in FSP API.
Add Set/GetFspMemoryInitUpdDataPointer() and Set/GetFspSiliconInitUpdDataPointer() API in FspCommonLib,
 so that core can set this UdpDataPointer and platform code may get UpdDataPointer easily.
Add UpdateMemSiUpdInitOffsetValue function in GenCfgOpt.py tool, so that the MemoryInitUpdOffset and SiUpdInitOffset is recorded.
Add missing EMBED comment in GenCfgOptUserManual.docx

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18123 6f19259b-4bc3-4df7-8a09-765794883524
2015-08-02 04:02:37 +00:00
Ard Biesheuvel 7669f73498 ArmVirtPkg: use 'auto' alignment and FIXED placement for XIP modules
Now that GenFw correctly propagates the minimum alignment of the ELF
input sections to the PE/COFF binary, we can simply select 'auto'
alignment in the FDF Rule section instead of tweaking it by hand.

Also add the FIXED FFS attribute to the module types that may execute
in place. This enables a newly added optimization in GenFfs that strips
redundant padding, preventing excessive waste of FV space if the section
alignment is considerable (i.e., 2 KB or 4 KB)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18122 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-31 08:24:18 +00:00
Eric Dong 00db1dfca2 UiApp: Move reset menu from Front Page to BMM Page.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18121 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-31 02:14:26 +00:00
Eric Dong b44b55a2df Remove the useless code to fix build failure caused by error depend on IntelFrameworkModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18120 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-31 02:12:54 +00:00
Eric Dong e5632f3d86 Fixed GCC tool chain build fail.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18119 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-31 01:21:50 +00:00
Harry Liebel 1bbb83b526 StdLib: Add support for AArch64
- Use some files from ARM version.
- Use NetBSD software floating point library to provide floating point
  operations not handled directly by hardware floating point enabled
  GCC compiler.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Daryl McDaniel <edk2-lists@mc2research.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18118 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 09:51:04 +00:00
Harry Liebel d799c02832 StdLib/LibC: Provide missing ARM symbols
Provide missing functionality by using files from LLVM.

Changes made:
- Formatting changes (tabs to spaces, DOS line endings etc).
- Simplified 'int_endianness.h' to work for our case.
- Added LLVM licence to the individual files.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Daryl McDaniel <edk2-lists@mc2research.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18117 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 09:50:58 +00:00
NetBSD project 3352b62beb StdLib/LibC: Add software floating point library from NetBSD
Floating point processing is not supported on ARM for UEFI. In order to
support UEFI applications in AppPkg we use this library to provide the
required functionality.

Changes as compared to the NetBSD version:
- Formatting changes (tabs to spaces, DOS line endings etc).
- Disable exceptions as described in the float_raise() function.
- Disable definition of 'Symbolic Boolean literals' in milieu.h.

Source originally from: NetBSD project
- Source: http://cvsweb.netbsd.org/bsdweb.cgi/?only_with_tag=MAIN
- Licensing and Copyright: http://www.netbsd.org/about/redistribution.html

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Daryl McDaniel <edk2-lists@mc2research.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18116 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 09:50:51 +00:00
Olivier Martin b393333538 StdLib: Added BaseStackLib for ARM architectures
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Daryl McDaniel <edk2-lists@mc2research.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18115 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 09:50:43 +00:00
Ruiyu Ni 5c13180cfc MdeModulePkg: Enhance PciBusDxe to handle high 32bit of MEM64 BAR returns 0
According to the PCI spec, when software writes all-one to BAR for size probing,
the value read back should be 0b1...10...0 after masking the BAR type bits.
But in real world, it's possible that certain device returns 0b0...01...10...0
for MEM64 BAR size probing: some bits in the high 32bit may be 0.
PciBus driver has the code to handle such case. However, it doesn't handle the
case that the high 32bit is totally 0. The patch is to handle the special case.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18114 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 06:40:36 +00:00
Eric Dong f2993c021d Enable NT32 platform to use new UiApp code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18113 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 03:45:09 +00:00
Eric Dong 5a673ab299 Legacy Boot Maintenance UI part code split from IntelFrameworkModulePkg/Universal/BdsDxe driver.
This is the legacy part of the old BdsDxe driver.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18112 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 03:43:14 +00:00
Eric Dong 143f0b1de8 UiApp code split from IntelFrameworkModulePkg/Universal/BdsDxe driver.
This is the UI part of the old BdsDxe driver, also remove the legacy boot option related code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18111 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-30 03:41:35 +00:00
Ard Biesheuvel 6ed41dadaa ArmPlatformPkg: remove obsolete ARM and AARCH64 platforms
Remove obsolete ARM and AARCH64 platforms so the maintainers can
focus on the ones that are still supported, which are:
- TC2 (ArmVExpress-CTA15-A7.dsc)
- Foundation model and Fast model emulators (ArmVExpress-FVP-AArch64.dsc)
- Juno (ArmJunoPkg/ArmJuno.dsc)
- Cortex-A15 MPcore RTSM (ArmVExpress-RTSM-A15_MPCore)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18110 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 16:17:27 +00:00
Michael D Kinney b56750422f MdeModulePkg/PciBus: Simplify an complex if statement to pass VS2015
The logic in an if statement in PciIo is too complex and hard to understand
and make VS2015 build failure. The fix simplifies the logic.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18109 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 11:11:56 +00:00
Michael D Kinney 26c2edd51f MdeModulePkg/Variable: Fix VS2015 warning about uninitialized local var.
This fix is used to solve VS2015 warning "local variable is not initialized before use"

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18108 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 11:11:34 +00:00
Zhang Lubo 14e84fd888 MdeModulePkg: Fix the issue cannot boot to UEFI Network after reset
DHCP4 service allows only one of its children to be configured
in the active state,If the DHCP4 D.O.R.A started by IP4 auto
configuration and has not been completed, the Dhcp4 state machine
will not be in the right state for the PXE to start a new round
D.O.R.A., so we need to switch it's policy to static.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18107 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 06:37:48 +00:00
Star Zeng 94dfaa233c Vlv2TbltDevicePkg: Exclude CapsuleX64 from IA32 build
CapsuleX64 is for 64bits capsule data access in PEI phase,
it is only needed for X64 DXE build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Tim He <tim.he@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18106 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 05:59:50 +00:00
Star Zeng eb63c77b8e MdeModulePkg: Include CapsuleX64 in MdeModulePkg.dsc [Components.X64]
It was forgotten to be included in MdeModulePkg.dsc when created.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18105 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 05:58:20 +00:00
Zhang Lubo ac99793b73 NetworkPkg: Fix the issue cannot boot to UEFI Network after reset
DHCP4 service allows only one of its children to be configured
in the active state,If the DHCP4 D.O.R.A started by IP4 auto
configuration and has not been completed, the Dhcp4 state machine
will not be in the right state for the PXE to start a new round D.O.R.A.
so we need to switch it's policy to static.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18104 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-29 04:10:09 +00:00
Ard Biesheuvel 15c9b25e5d ArmVirtPkg: implement DT-based ArmGicArchLib
Since it is arguably incorrect to infer the GIC revision from CPU
ID and GIC feature registers on platforms that describe the GIC in
the device tree, this implements the library class ArmGicArchLib
tailored for such platforms.

The supported GIC revision is retrieved from the dynamic PCD that
is set based on the GIC DT node.

This means this library can only execute post DXE core, but this is
not a problem for any of the virt platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18102 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:45:36 +00:00
Ard Biesheuvel ae26410e28 ArmVirtPkg: record GIC revision in dynamic PCD
In order to allow a ArmGicArchLib to be implemented that returns
the supported GIC revision based on the device tree, add handling
to VirtFdtDxe to record the GIC revision at DT parsing time.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18101 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:45:25 +00:00
Ard Biesheuvel f94522c823 ArmPkg: cache detected revision in ArmGicArchLib
Instead of inferring the GIC revision from the CPU id registers
and the presence/availability of the system register interface
upon each invocation, move the logic to a constructor and cache
the result.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18100 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:45:10 +00:00
Ard Biesheuvel e9e9c7e8a4 ArmPkg: copy ArmGicArchLib to ArmGicArchSecLib
Clone ArmGicArchLib into a SEC phase specific ArmGicArchSecLib
so that we can modify the former in a subsequent patch to cache
the GIC revision in a global variable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18099 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:44:58 +00:00
Ard Biesheuvel 8d13298b80 ArmPkg: split off ArmGicArchLib from ArmGicLib
The current implementation of ArmGicGetSupportedArchRevision ()
that is used by all ARM platforms is entirely stateless (in order
to support being executed from flash) so it needs to interrogate
the hardware for the supported GIC revision upon each invocation.

However, this statelessness is only needed for SEC type modules;
in all other cases, we could easily determine the GIC revision once,
and store the result in a global variable.

In preparation of having separate early and normal versions, this patch
introduces the ArmGicArchLib library class and default implementation,
and moves the existing ArmGicGetSupportedArchRevision () into it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18098 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:44:44 +00:00
Ard Biesheuvel bce29e3059 ArmPkg: merge ArmGicV[23]Lib.h into ArmGicLib.h
Before splitting off ArmGicArchLib and moving it out of
ArmPkg/Drivers/ArmGic into ArmPkg/Library, make sure that the
GIC specific declarations it depends on are not hidden away in
local headers "GicV2/GicV2Lib.h" and "GicV3/GicV3Lib.h".

So merge them with <Library/ArmGicLib.h>. This is entirely
appropriate, since this is not a header that declares a public
interface into ArmGicLib, but defines implementation internals.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18097 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:44:27 +00:00
Jaben Carsey 983fffd431 ShellPkg: prevent Close call when Open failed
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Tapan Shah <tapandshah@hp.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18096 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 20:22:26 +00:00
Laszlo Ersek 6394c35a7d OvmfPkg: fix conversion specifiers in DEBUG format strings
Cc: Scott Duplichan <scott@notabs.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Reported-by: Scott Duplichan <scott@notabs.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Build-tested-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18095 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 18:33:23 +00:00
Yao, Jiewen 00899456b8 FspNotifyDxe need handle >4G memory.
The FSP API is always 32bit, but FspNotifyDxe might load to >4G memory. In order to make thunk work, we need reload FspNotifyDxe to <4G memory.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18094 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 07:26:57 +00:00
Yao, Jiewen 71a6022f69 Bug fix in PatchFv.py for GCC build in IntelFspPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18093 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 07:24:48 +00:00
Yao, Jiewen 70c7664cd3 Add Secure MOR implementation.
Add a new module MemoryOverwriteRequestControlLock to register VarCheck handler to  enforce MorLock Policy.
Only SMM version is added because MOR is only supported in SMM variable case. 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Chao Zhang" <chao.b.zhang@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18092 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 07:20:58 +00:00
Yao, Jiewen 5c61c5cfc8 Downgrade one debug message level in DxeTpm2MeasureBootHandler from EFI_D_ERROR to EFI_D_INFO.
No TPM2 is considered as valid case. For example, a platform may only have TPM1.2, without TPM2.0 So this is NOT an ERROR message, but more an INFO message.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Chao Zhang" <chao.b.zhang@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18091 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28 06:58:47 +00:00