Change our resolution for the previously unused CpuExceptionHandlerLib
from the null implementation to the newly added implementation specific
to AARCH64 and ARM. This is needed since our CpuDxe will start using it
in a subsequent patch.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
In UEFI2.6, CapturePtr's in the Captures array returned by MatchString
are to be separatedly allocated so that they can be freed by the
caller.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Cecil Sheng <cecil.sheng@hpe.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This is an emergency fix for UINT64 multiplications and divisions not
being done with the right BaseLib functions -- they break Ia32 builds.
Fixes: 30ed3422ab
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Introduce ARM and AArch64 instances of the CpuExceptionHandlerLib which
provides exception handling and registration of handlers regardless of
execution phase.
Two variants of the ArmExceptionLib are provided: one where exception
handlers reside within the module (meeting appropriate architectural
alignment requirements for the vector table) and another one that will
relocate a copy of thee xception handlers to an address specified by
PcdCpuVectorBaseAddress. The ArmRelocateExceptionLib is intended for use
in cases where ArmExceptionLib is too large for the application
(uncompressed XIP images) as driven by the vector table alignment padding.
The AArch64 build of this library supports execution at EL1, EL2, and EL3
exception levels.
Tested on ARM, and AArch64 with SEC, DXE Core, and CpuDxe modules.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system
register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
ConSplitter's Absolute Pointer should scale virtual device's resolution like what Simple Pointer do.
Before this change, caller will get Virtual device's resolution but physical device's current point.
This change let caller get Virtual device's resolution with virtual device's current point.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Derek Lin <derek.lin2@hpe.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This patch makes Shell support -nonesting invocation option. This option
specifies that EFI_SHELL_PROTOCOL.Execute API nesting of a new Shell
instance is optional and dependent on the 'nonesting' Shell environment
variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Jim Dailey <Jim_Dailey@Dell.com>
The HTTP Boot driver have some UEFI driver model problems which will make the
code ASSERT when it's disconnected.
First, the driver opens the HttpSb protocol BY_CHILD without BY_DRIVER attribute.
So the driver binding stop won't be called when HTTP driver is disconnected, so
a child handle is left and made HTTP driver binding stop function goes into error.
This patch remove this unnecessary OpenProtocol and only unload the HII from when
both the IP4 and IP6 stack have been stopped completely.
The second issue is the HTTP boot driver always use the driver's image handle as
it's driver binding handle, it's not correct. HTTP Boot driver provides 2 separate
driver binding protocols from IP4 and IP6 stack, so it has 2 driver binding handle.
So this patch fix the code to use correct driver binding handle when create/open
a HTTP child handle.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Remove the ASSERT code that may be triggered in LegacyBootMaintUiLib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Remove the ASSERT in UI code that may be triggered,
and clean up the useless code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
In DriverSampleInit, has installed the configAccess protocol to
the DriverHandle[1], but don't uninstall it in DriverSampleUnload.
Now uninstall the configAccess protocol.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
this patch add new feature to support override PCD value on the command
line. The value from the command line is the highest priority.
1.Add option(--pcd) to support both PcdName and TokenSpaceGuild.PcdName
2.For void* type PCD, use following format:
cstring PCD: --pcd PcdName="string"
unicodestring PCD: --pcd PcdName=L"string"
CArray PCD: --pcd PcdName=B"{0x1, 0x2}"
3.Build Report, use *B to show the PCD value was overridden in the
command line.
4.Error Condition:
Report error if the PCD is not found
Report error if the PcdName is found under multiple different TokenSpaceGuid
Report error if PCD value syntax is incorrect
Report error if void* type PCD value exceed its max size
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Current implementation only supports legacy region of 440 chip.
When QEMU is launched in Q35 mode using CSM enabled OVMF image,
LegacyBios driver fails to start due to the legacy region
[0xC0000, 0xFFFFF] cannot be written.
v2:
* just updates the comments.
v3:
* uses PcdOvmfHostBridgePciDevId as Jordan suggested.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Justen Jordan <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This patch fixes the assumed invalid command to start recent versions
of cx_freeze on Windows, which are python and not Windows
executables. To launch them correctly, the '$(PYTHON_HOME)\python'
prefix has been added, so that Python can interpret the tool.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
Add DEST_DIR_OUTPUT and DEST_DIR_DEBUG into AutoGenObject macro dict.
Because some module (eg: BaseUefiCpuLib) may use this macro in the make
file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
When someone doesn't know where to find or what to do with
vsvars32.bat, get_vsvars.bat can be used.
CC: Yonghong Zhu <yonghong.zhu@intel.com>
CC: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Peter Kirmeier <topeterk@freenet.de>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Commit 7c50b34343 introduced
PcdMaxPeiPerformanceLogEntries16 to support > 256 PEI performance log
entries, but its PROMPT&HELP STR were forgotten to be added into *.uni.
Commit 7c50b34343 also updated
PcdMaxPeiPerformanceLogEntries HELP STR.
This patch is to add PcdMaxPeiPerformanceLogEntries16 PROMPT&HELP STR and
update PcdMaxPeiPerformanceLogEntries HELP STR in *.uni.
Cc: Shumin Qiu <shumin.qiu@intel.com>
Cc: Cinnamon Shia <cinnamon.shia@hpe.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Shumin Qiu <shumin.qiu@intel.com>
Reviewed-by: Cinnamon Shia <cinnamon.shia@hpe.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This patch is used to fix the potential system hang
caused by the NULL 'time' parameter usage.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Long Qin <qin.long@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: David Woodhouse <David.Woodhouse@intel.com>
Support multiple PL061 controllers. If platform gpio driver couldn't be
found, PL061 gpio driver will continue to load PcdPL061GpioBase as the
register base.
It could be compatible with the use case of current PL061 gpio driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
EmbeddedGpio only supports one gpio controller in one platform. Now
create PLATFORM_GPIO_CONTROLLER to support multiple gpio controllers
in one platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
The original bug is only consider int format of PcdSize, but forgot the
Hex format. The fix is use the already exist variable PCD.PcdBinSize
which done to translate PCD size cover both format.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add top level MSR include file that includes the Architecural MSR
include file and all family specific MSR files from the Msr
subdirectory
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Add Pentium M MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-18.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Add Xeon Processor D MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-13.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Add Atom MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-3.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
OpenSSL 1.0.2g was released with several severity fixes at
01-Mar-2016(https://www.openssl.org/news/secadv/20160301.txt).
Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to
catch the latest release 1.0.2g.
(NOTE: RT4175 from David Woodhouse was included in 1.0.2g. The
new-generated patch will remove this part. And the line
endings were still kept as before in this version for
consistency)
CC: Ting Ye <ting.ye@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long <qin.long@intel.com>
Reviewed-by: David Woodhouse <David.Woodhouse@intel.com>
Until we fix the git repository to store line endings properly and then
just check them out in the appropriate form for the platform, let's make
process_files.sh convert the opensslconf.h to DOS line endings when it
creates it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
Unlike Linux on x86, which typically honors the PCI configuration performed
by the firmware, Linux on ARM assumes that the PCI subsystem needs to be
configured from scratch. This is not entirely unreasonable given the
historical background of embedded systems using very basic bootloaders,
but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the
server space. For this reason, PCI support in the arm64 kernel running under
ACPI is likely to move to the x86 model of honoring the PCI configuration
done by the firmware.
So let's align with that in our DT based configuration as well, and set the
/chosen/linux,pci-probe-only property to 1 in the Device Tree before we
hand it to the OS.
In case we are exposing an emulated VGA PCI device to the guest, which may
subsequently get exposed via the Graphics Output protocol and driven as an
efifb by the OS, this ensures the PCI resource allocations for the framebuffer
are not overridden, since that would cause the framebuffer to stop working.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Ard Biesheuvel
Qiu Shumin
Cecil Sheng
Laszlo Ersek
Cohen, Eugene
Derek Lin
Fu Siyuan
Jiaxin Wu
Dandan Bi
Yonghong Zhu
Ruiyu Ni
Marvin Haeuser
Peter Kirmeier
Star Zeng
Haojian Zhuang
Michael Kinney
Qin Long
David Woodhouse