Commit Graph

6 Commits

Author SHA1 Message Date
Ray Ni c16f02f776 CpuPageTableLib: Avoid treating non-leaf entry as leaf one
Today's logic wrongly treats the non-leaf entry as leaf entry and
updates its paging attributes.

The patch fixes the bug to only update paging attributes for
non-present entries or leaf entries.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
Ray Ni 9cb8974f06 CpuPageTableLib: Split the page entry when LA is aligned but PA is not
When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.

The patch fixes the bug.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
Ray Ni 13a0471bfd CpuPageTableLib: Refactor the logic
The patch replaces
  LinearAddress + Offset == RegionStart
with
  ((LinearAddress + Offset) & RegionMask) == 0

The replace should not cause any behavior change.

Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
  because the lower "BitStart" bits of RegionStart are all-zero,
  all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
  Because all lower "BitStart" bits of RegionMask is all-one and
  bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.

2. In following loops of the while, even RegionStart is increased
  by RegionLength, the lower "BitStart" bits are still all-zero.
  So the two expressions still semantically equal to each other.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
Ray Ni bf334513b3 CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in Mask
To reproduce the issue:
  UINTN               PageTable;
  VOID                *Buffer;
  UINTN               PageTableBufferSize;
  IA32_MAP_ATTRIBUTE  Attribute;
  IA32_MAP_ATTRIBUTE  Mask;
  RETURN_STATUS       Status;

  Attribute.Uint64       = 0;
  Mask.Uint64            = 0;
  PageTableBufferSize    = 0;
  PageTable              = 0;
  Buffer                 = NULL;
  Attribute.Bits.Present = 1;
  Attribute.Bits.Nx      = 1;
  Mask.Bits.Present      = 1;
  Mask.Uint64            = MAX_UINT64;

  //
  // Create page table to cover [0, 10M)
  //
  Status = PageTableMap (
             &PageTable, PagingMode, Buffer, &PageTableBufferSize,
             0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_BUFFER_TOO_SMALL);
  Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
  Status = PageTableMap (
             &PageTable, PagingMode, Buffer, &PageTableBufferSize,
             0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_SUCCESS);

  //
  // Change the mapping for [0, 4KB)
  // No change actually. Just clear Nx bit in Mask.
  //
  Mask.Bits.Nx        = 0;
  PageTableBufferSize = 0;

  Status = PageTableMap (
             &PageTable, PagingMode, NULL, &PageTableBufferSize,
             0, (UINT64)SIZE_4KB, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_SUCCESS); // FAIL!!

The root cause is when comparing the existing mapping attributes
against the requested one, Mask is not used but it should be used.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
Ray Ni f336e30ba1 UefiCpuPkg/CpuPageTableLib: Return error on invalid parameters
When LinearAddress or Length is not aligned on 4KB, PageTableMap()
should return Invalid Parameter.

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00
Ray Ni 75e3c2435c UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structs
The lib includes two APIs:
* PageTableMap
  It creates/updates mapping from LA to PA.
  The implementation only supports paging structures used in 64bit
  mode now. PAE paging structure support will be added in future.

* PageTableParse
   It parses the page table and returns the mapping relations in an
  array of IA32_MAP_ENTRY.

It passed some stress tests. These test code will be upstreamed in
other patches following edk2 Unit Test framework.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2022-08-09 07:08:05 +00:00