30996 Commits

Author SHA1 Message Date
Savva Mitrofanov
d0b4d95eff Revert "UefiCpuPkg: Enhance logic in InitializeMpExceptionStackSwitchHandlers"
This reverts commit 4b7bd4c591a81a290b31e9d1a94c4b8be787989e, because it
breaks IA32 targets, at least for XCODE5, CLANGPDB and CLANGDWARF
toolchains

Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
2023-04-28 16:55:39 +03:00
Savva Mitrofanov
98937be856 RedfishPkg/BaseUcs2Utf8Lib: Fix out of bounds shift in UTF8ToUCS2Char
Missing masks leads to shift out of bounds. Also there is no need to
construct CHAR16 using cast to CHAR8 buffer, better to use native endian
by assigning data directly into Ucs2Char variable

Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
Reviewed-by: Marvin Häuser <mhaeuser@posteo.de>
2023-04-28 16:55:39 +03:00
Savva Mitrofanov
9a53125a35 MdePkg/BasePcdLibNull: Remove ASSERT from LibPcdGetSize, LibPcdGetExSize
GetSize routines should return zero size when checking Token existence

Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
Reviewed-by: Vitaly Cheptsov <vit9696@protonmail.com>
2023-04-28 16:55:39 +03:00
Vitaly Cheptsov
b88fb7469c OvmfPkg/DxePciLibI440FxQ34: Add UefiBootServicesTableLib dependency
In case PlatformBootManagerLib does not have PciLib dependency,
we need to explicitly depend on UefiBootServicesTableLib.
Otherwise UefiBootServicesTableLib may not be constructed before
DxePciLibI440FxQ35, which uses a constructor-less PcdLib that directly
accesses gBS.

This can be viewed as a bug in the current implementation of BaseTools,
namely GetModuleLibInstances. This function drops all constructor-less
dependencies from the dependency resolution list to avoid dependency
cycles, which at the same time causes issues like above.

To properly fix the issue one should go over each library with
constructors and for each its dependency without constructors add all
the secondary dependencies that do have constructors. While doable,
it may cause considerable performance issues and is thus not done
in this patch.

Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
2023-04-28 16:55:39 +03:00
Savva Mitrofanov
99b1eacd81 UefiPayloadPkg/PchSmiDispatchSmm: Add missing EFIAPI modifiers
Added missing EFIAPI modifier to SmmSwDispatcher function which passed into gSmst->SmiHandlerRegister routine.

Signed-off-by: Savva Mitrofanov <sk.mitrofanov@ispras.ru>
Reviewed-by: Vitaly Cheptsov <cheptsov@ispras.ru>
2023-04-28 16:55:39 +03:00
Vitaly Cheptsov
29701b6bd9 BaseTools: Allow .text relocations in CLANGDWARF toolchain
UefiCpuPkg modules like ExceptionHandlerAsm.nasm require relocations
to .text or PIC as they use instructions like mov or bt against
external symbols:

1. mov     rax, ASM_PFX(CommonInterruptEntry)
2. mov     rax, HookAfterStubHeaderEnd
3. bt      [ASM_PFX(mErrorCodeFlag)], ecx
4. mov     [rcx + (@VectorNum - HookAfterStubHeaderBegin)], al

It is not easily possible to rewrite 3/4 cases without involving
more registers or more commands, and EDK II has never targeted
read-only .text at load time, only at runtime.

Change the defaults to let OVMF compile by CLANGDWARF as per:
https://lists.llvm.org/pipermail/llvm-dev/2017-March/111441.html

Signed-off-by: Vitaly Cheptsov <cheptsov@ispras.ru>
2023-04-28 16:55:39 +03:00
Mikhail Krichanov
4539a64818 BaseTools: Fix for NOOPT CLANG38 compilation with clang-13
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3715

We must treat not only R_X86_64_PLT32 as R_X86_64_PC32
(https://github.com/torvalds/linux/commit/
b21ebf2fb4cde1618915a97cc773e287ff49173e),
but also treat R_386_PLT32 relocation as R_386_PC32
(https://github.com/torvalds/linux/commit/
bb73d07148c405c293e576b40af37737faf23a6a).

Signed-off-by: Mikhail Krichanov <krichanov@ispras.ru>
2023-04-28 16:55:39 +03:00
Goldfish64
0ddc355593 OvmfPkg/SioBusDxe: Add PS/2 mouse support
SioBusDxe by default does not create a device for PS/2 mice, this patch adds that device.
2023-04-28 16:55:39 +03:00
Vitaly Cheptsov
77f168939c ShellPkg: Add support for input with separately reported modifiers
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2510

Some firmwares:
- Report Shift modifier even when they report upper-case unicode letter.
- Report Ctrl modifier with "shifted" UniChar (i.e. X - 'A' + 1).

This change provides support for these firmwares preserving the compatibility
with the previous input handling.

Signed-off-by: Michael Belyaev <usrsse2@icloud.com>
Reviewed-by: Vitaly Cheptsov <vit9696@protonmail.com>
2023-04-28 16:55:39 +03:00
Mikhail Krichanov
0b691c8274 CryptoPkg/OpensslLib: Fix build for XCODE5 compiler on macOS
REF: https://edk2.groups.io/g/devel/message/88179

A build of CryptoPkg with XCODE5 on macOS is now trying to include
Availability.h, which isn't found. Seems the problem is in condition
logic inside openssl/include/crypto/rand.h

Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
2023-04-28 16:55:39 +03:00
Mikhail Krichanov
9760d73de3 MdePkg: DebugLib: Compilation fix for clang-13
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3704

build -a X64 -t CLANG38 -b RELEASE -p OvmfPkg/OvmfPkgX64.dsc
results in
UDK/MdeModulePkg/Library/UefiBootManagerLib/BmBoot.c:1284:31:
error: variable 'Status' set but not used
[-Werror,-Wunused-but-set-variable]

Signed-off-by: Mikhail Krichanov <krichanov@ispras.ru>

MdePkg/DebugLib(PerformanceLib): Fix "unused-but-set-variable" warning

The current definitions of DEBUG_CODE_BEGIN() and DEBUG_CODE_END() use 
the local
variable __DebugCodeLocal as an attempt to track parity. If 
DEBUG_CODE_END() is
used without a preceding DEBUG_CODE_BEGIN(), __DebugCodeLocal will not 
have been
declared and a compilation error will be issued. The mutations of the 
variable
are not used to track nesting or such. As the value of this variable is 
never
actually used, recent Clang versions issue a "unused-but-set-variable" 
warning
for it.

To solve this, re-define __DebugCodeLocal as a BOOLEAN that is always 
FALSE and
use it in a do-while loop condition as done explicitly in many places. 
Like the
previous solution, DEBUG_CODE_END() cannot be used without 
DEBUG_CODE_BEGIN(),
as __DebugCodeLocal will be not have been defined.

Signed-off-by: Marvin Häuser <mhaeuser@posteo.de>
2023-04-28 16:55:39 +03:00
Mikhail Krichanov
2cdff1206e OvmfPkg/PlatformInitLib: Corrects initializers to fix NOOPT build
Fixes OvmfPkg build using XCODE5, CLANGPDB and CLANGDWARF toolchains
for NOOPT target

Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
2023-04-28 16:55:39 +03:00
Mikhail Krichanov
05702eddbd Ext4Pkg: Various improvements based on Sydr fuzzing results.
Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
2023-04-28 16:55:39 +03:00
Savva Mitrofanov
584fcbf4dd Ext4Pkg: Add EDK II Ext4 package
Adds a Pedro Falcato's UEFI EXT4 filesystem driver that implements the EFI_FILE_PROTOCOL and EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.

Signed-off-by: Savva Mitrofanov <savvamtr@gmail.com>
2023-04-28 16:55:39 +03:00
Sunil V L
f80f052277 OvmfPkg/RiscVVirt: Add Stack HOB
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4350

Currently, stack HOB is not created for the stack memory. This causes
stack memory to be treated as free memory and any memory allocation which
happens at this address causes random memory corruption. Fix this by
creating the stack HOB which marks the memory as BS data.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reported-by: Andrei Warkentin <andrei.warkentin@intel.com>
Tested-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-03-01 15:08:07 +00:00
MarsX Lin
1eeca0750a UefiPayloadPkg: remove the change that get platform specific logic
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4241

Since UefiPayloadPkg had supported multiple firmware volume,
remove the platform specific logic via protocol

Cc: Ray Ni <ray.ni@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Cc: Gua Guo <gua.guo@intel.com>
Reviewed-by: James Lu <james.lu@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>

Signed-off-by: MarsX Lin <marsx.lin@intel.com>
2023-02-23 07:47:12 +00:00
Sunil V L
bc82574de4 OvmfPkg/RiscVVirt: Fix SCT memory allocation test case failure
Fix the UEFI memory range calculation by including the correct
stack memory range. Without this fix, SCT hangs in MemoryAllocation
test cases which call AllocateAddress().

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Reported-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-02-23 05:02:15 +00:00
Sunil V L
2c5961cccf BaseTools/tools_def.template: Update -march parameter for RISC-V
Replace rv64imafdc with rv64gc so that it works for gcc 12.

"g" means imafd in gcc < 12 and imafd_zifencei_zicsr in gcc >= 12.
So, replacing rv64imafdc with rv64gc will work for both gcc <12
and gcc >=12.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-02-23 03:56:05 +00:00
Joey Vagedes
02fcfdce1e BaseTools: Update WindowsVsToolChain plugin
This patch updates edk2-pytool-library dependency to v0.14.0, which has
an interface change to FindWithVsWhere. The BaseTools plugin uses this
function, so it is being updated to account for the interface change.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>

Signed-off-by: Joey Vagedes <joeyvagedes@microsoft.com>
Acked-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-02-16 18:54:33 +00:00
Sunil V L
5c551d6d91 Maintainers.txt: Add entry for OvmfPkg/RiscVVirt
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RiscVVirt is created to support EDK2 for RISC-V qemu
virt machine platform. Add maintainer entries.

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-16 05:53:28 +00:00
Sunil V L
92b27c2e6a OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add infrastructure files to build edk2 for RISC-V qemu virt machine.

- It follows PEI less design.
- EDK2 for qemu virt is booted in S-mode as a payload for M-mode FW
- Leveraged from ArmVirtQemu

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
e1aaef001f OvmfPkg/RiscVVirt: Add SEC module
Add the SEC module for RISC-V Qemu virt machine support.
It uses the PEI less design.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-16 05:53:28 +00:00
Sunil V L
a43a62f9b0 OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module
Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL
to add the translation for IO access. This is copied from
ArmPciCpuIo2Dxe driver.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
6d5ae344cd OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library
Qemu NOR flash driver needs this library. Add this
library for RISC-V leveraged from SbsaQemu.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-16 05:53:28 +00:00
Sunil V L
c126e3588d OvmfPkg/RiscVVirt: Add ResetSystemLib library
RISC-V Qemu virt uses SBI calls to implement the reset.
Add the base class library.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
6720b8e46f OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library
Add the PrePiHobListPointerLib required for RISC-V Qemu Virt machine
since it follows PEIless design.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-16 05:53:28 +00:00
Sunil V L
d78df93863 OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library
RISC-V Qemu Virt platfform needs the PlatformBootManagerLib similar
to the one in ArmVirtPlatform. Add the library in OvmfPkg/RiscVVirt
leveraging the one from Arm.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
f13264b340 ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

PlatformHasAcpiDtDxe is required by other architectures also.
Hence, it is moved to OvmfPkg. So, update the consumers of this
module with the new location.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-16 05:53:28 +00:00
Sunil V L
09cd17b0de ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This module is required by other architectures like RISC-V.
Hence, move this to OvmfPkg.

Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
a7dec790dc UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V register names do not follow the EDK2 formatting.
So, add it to ignore list for now.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Ray Ni <ray.ni@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
c27cdc941d UefiCpuPkg: Add CpuDxeRiscV64 module
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe
and added the RISCV_EFI_BOOT_PROTOCOL support.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
98fa877efd UefiCpuPkg: Add CpuTimerDxeRiscV64 module
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This DXE module initializes the timer interrupt handler
and installs the Arch Timer protocol.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ray Ni <ray.ni@Intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
705c3469b5 UefiCpuPkg: Add BaseRiscV64CpuTimerLib library
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add the RISC-V instance of the TimerLib.

This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ray Ni <ray.ni@Intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
cbac2c74e8 UefiCpuPkg: Add BaseRiscV64CpuExceptionHandlerLib
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add Cpu Exception Handler library for RISC-V. This is copied
from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ray Ni <ray.ni@Intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
d6017bca19 UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add this protocol GUID definition and the header file required.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Acked-by: Ray Ni <ray.ni@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
76e956547e MdePkg: Add BaseRiscVSbiLib Library for RISC-V
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This library is required to make SBI ecalls from the S-mode EDK2.
This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
550f196e82 MdePkg/BaseLib: RISC-V: Add few more helper functions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Few of the basic helper functions required for any
RISC-V CPU were added in edk2-platforms. To support
qemu virt, they need to be added in BaseLib.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-16 05:53:28 +00:00
Sunil V L
8aeb405466 MdePkg/Register: Add register definition header files for RISC-V
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.

Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-16 05:53:28 +00:00
Robert Phelps
38da9606f7 MdePkg: Added Call for AfterReadyToBoot Event
In the function EfiSignalEventReadyToBoot, Code was added to also create,
signal, and close the AfterReadyToBoot event.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Robert Phelps <robert@ami.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-02-15 12:34:20 +00:00
Robert Phelps
419c0aafa6 MdePkg: Add After Ready To Boot Event Definition from UEFI 2.9
Add After Ready To Boot Event Definitions

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Robert Phelps <robert@ami.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-02-15 12:34:20 +00:00
lijun10x
77d6772708 MdeModulePkg/Library: PcdAcpiS3Enable set FALSE cause Assert
Some platforms don't support S3 with PcdAcpiS3Enable set as False.
Debug mode bios will ASSERT at this time as Follows.
ASSERT_RETURN_ERROR (Status = Out of Resources)
DXE_ASSERT!: Edk2\MdePkg\Library\BaseS3PciSegmentLib\S3PciSegmentLib.c
(61): !(((INTN)(RETURN_STATUS)(Status)) < 0)

Steps to reproduce the issue:
1.Set PcdAcpiS3Enable to FALSE.
2.Build the bios in debug mode.
3.Power on and Check the serial log.
Note: Prerequisite is that S3PciSegmentLib is Called and
the caller's code is run.

Root Cause:
S3PciSegmentLib call S3BootScriptLib controlled by PcdAcpiS3Enable.
If PcdAcpiS3Enable set as false, S3BootScriptLib will return error
status(Out of Resources).
S3PciSegmentLib will ASSERT if S3BootScriptLib return error.

Solution:
Make S3BootScriptLib return success if PcdAcpiS3Enable was disabled,
which behave as a null S3BootScriptLib instance which just return success
for no action is required to do.

Signed-off-by: JunX1 Li <junx1.li@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sunny Wang <sunny.wang@arm.com>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: G Edhaya Chandran <edhaya.chandran@arm.com>
Cc: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
2023-02-15 06:42:12 +00:00
Stuart Yoder
68c1bedbf2 MdeModulePkg/Variable: Attribute combination should return EFI_UNSUPPORTED
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4341

Commit 21320ef66989 broke some tests in the AuthVar_Conf test
in edk2-test.  There are 2 testcases that invoke SetVariable
with the following attribute value:

(EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS)

EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and the UEFI spec
says this should return EFI_UNSUPPORTED.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Sunny Wang <Sunny.Wang@arm.com>

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Sunny Wang <sunny.wang@arm.com>
2023-02-15 04:29:36 +00:00
devel@edk2.groups.io
090642db7a MdeModulePkg/EsrtFmpDxe: Support multiple devices with 0 HardwareInstance
Skip error check if HardwareInstance is 0 as this either means that
FmpVersion < 3 and not supported or,
"A zero means the FMP provider is not able to determine a
unique hardware instance number or a hardware instance number
is not needed." per UEFI specification.

As the FmpInstances are merged and HardwareInstance is not used
remove error check in this case.

Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-15 01:52:59 +00:00
Abner Chang
f9c6b5134e MdeModulePkg/Pci: Display more information of PCIe devices
In V4: Update the copyright to 2023.
In V3: Add AMD copyright.
In V2: Remove the signed-off-by: Abner Chang

Display PCIe Vendor ID and Device ID in DEBUG message.

Signed-off-by: Jiangang He <jiangang.he@amd.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Garrett Kirkendall <garrett.kirkendall@amd.com>
Cc: Abner Chang <abner.chang@amd.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-15 01:07:18 +00:00
Dionna Glaze
1b5420e807 OvmfPkg/AmdSevDxe: Close mAcceptAllMemoryEvent
This event should only trigger once. It should be idempotent, but the
allocation of the memory map itself is observable and can cause
ExitBootServices to fail with a modified map key.

Cc: Thomas Lendacky <Thomas.Lendacky@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Michael Roth <michael.roth@amd.com>

Signed-off-by: Dionna Glaze <dionnaglaze@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-15 00:08:00 +00:00
Dionna Glaze
f67ec87704 OvmfPkg: Fix SevMemoryAcceptance memory attributes
The hard-coded attributes for the re-added memory space should instead
forward the replaced descriptor's capabilities.

Tested on Linux with efi=debug. Prior to this change, an 8GiB VM running
a kernel without unaccepted memory support shows this entry

efi: mem94: [Conventional|   |  |CC|  |  |  |  |  |  |   |  |  |  |  ]
range=[0x0000000100000000-0x000000023fffffff] (5120MB)

This does not have the cache capabilities one would expect for system
memory, UC|WC|WT|WB.

After this change, the same entry becomes

efi: mem94: [Conventional|   |  |CC|  |  |  |  |  |  |   |WB|WT|WC|UC]
range=[0x0000000100000000-0x000000023fffffff] (5120MB)

This has all the expected attributes.

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Michael Roth <michael.roth@amd.com>

Signed-off-by: Dionna Glaze <dionnaglaze@google.com>
[ardb: drop the EFI_MEMORY_CPU_CRYPTO flag - it isn't used anywhere else
       in EDK2 or Linux so it doesn't actually do anything, and it is
       unclear whether it is intended for use by the guest in the first
       place]
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
2023-02-15 00:08:00 +00:00
Michael Kubacki
540522fec0 .devcontainer/devcontainer.json: Add devcontainer file
Tianocore maintains container images in the tianocore/containers repo
and stores container images within the GitHub container registry.

https://github.com/tianocore/containers

This change adds a devcontainer.json file to the edk2 repo. This
file's metadata and settings to configurate a development container
for a given well-defined tool and runtime stack.

More information about the devcontainer.json file is available here:
https://containers.dev/implementors/json_reference/

This file is recognized by popular tools such as GitHub Codespaces
and VS Code. In VS Code in particular, it makes it much easier for
a user to be aware a dev container exists (via UI notifications)
and to load the container.

A minimal number of VS Code extensions are specified that are useful
for edk2 development or to assist in complying with CI checks in
place in edk2.

Cc: Andrew Fish <afish@apple.com>
Cc: Chris Fernald <chris.fernald@outlook.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Oliver Steffen <osteffen@redhat.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-14 01:28:13 +00:00
Michael Kubacki
b3f321f2d7 .mergify/config.yml: Remove rebase_fallback attribute (deprecated)
PR builds and CI are currently broken due to a mergify brownout
today because edk2 uses the `rebase_fallback` attribute of the
`queue` action.

Message from Mergify/Summary:

```
  The configuration uses the deprecated rebase_fallback attribute
  of the queue action.

  A brownout is planned on February 13th, 2023.

  This option will be removed on March 13th, 2023.
  For more information: https://docs.mergify.com/actions/queue/
```

Therefore, this change removes the attribute per the guidance in
the following changelog message to retain existing behavior.

https://changelog.mergify.com/changelog/rebasefallback-is-deprecated

```
  The option rebase_fallback is now deprecated and should not be
  used anymore.

  Mergify will always report errors in the future if a rebase merge
  is impossible.
```

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Rebecca Cran <rebecca@bsdio.com>
2023-02-13 15:58:21 -08:00
Weipu Zhu
93a21b465b MdePkg: Add NVMe boot partition header definition
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4304

Add NVMe boot partition header definition to NVMe.h
according to NVMe spec 2.0.

Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Weipu Zhu <weipu.zhu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-10 03:14:12 +00:00
Weipu Zhu
069703228c MdePkg: Add RPMB related commands and DCB definition for NVMe
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4303

Add RPMB(Replay Protected Memory Block) access commands,
result and DCB(Device Configuration Block) definition for
NVMe according to the NVMe spec 2.0.

Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Weipu Zhu <weipu.zhu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
2023-02-10 03:14:12 +00:00