Code logic ensures that both pointers 'DriverInfoData' and 'AllocInfoData'
will not be NULL when they are used.
Add ASSERTs as warning for cases that will not happen.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This change is to avoid UEFI SCT failure as UEFI SCT has no knowledge
about how to accessing a EMMC RPMB partition.
The user needs to access RPMB partition should get access through
EFI_SD_MMC_PASS_THRU protocol with authentication key & mac.
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
We have to upgrade the TPL level used by SdMmc stack because the
following flow:
DiskIo2ReadWriteDisk() in logical partition -> PartitionReadBlocksEx()
in logical partition at TPL callback level -> ProbeMediaStatusEx()
with sync request -> DiskIo2ReadWriteDisk() in physical partition ->
waiting for async task completion.
if the low layer driver doesn't run at TPL_NOTIFY level, it will have
no time to trigger async task and cause system hang.
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Provides services to record memory profile of multilevel caller.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
1. Produce SMM memory profile protocol.
2. Consume PcdMemoryProfilePropertyMask to support disable recording
at the start.
3. Consume PcdMemoryProfileDriverPath to control which drivers need
memory profile data.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
1. Implement include GetRecordingState/SetRecordingState/Record for
memory profile protocol.
2. Consume PcdMemoryProfilePropertyMask to support disable recording
at the start.
3. Consume PcdMemoryProfileDriverPath to control which drivers need
memory profile data.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Current memory profile feature:
1. Shows which line of code calls gBS->AllocateXXX(). But most entries
are from MemoryAllocationLib.
2. Records at the start.
3. Records all modules.
Enhanced memory profile feature:
1. User can know which line of code calls AllocateXXX() API instead of
gBS->Allocate().
2. User can know which line of code calls a specific API that will call
AllocateXXX().
3. User can know total memory allocated by a specific line of code.
4. User can configure to record single module.
5. User can configure when to enable recording.
6. User can know RVA<->Symbol (Function, Source, Line).
For the enhanced memory profile feature,
1. Extend MEMORY_PROFILE_DRIVER_INFO to include PdbString.
2. Extend MEMORY_PROFILE_ALLOC_INFO to include ActionString.
3. Extend MEMORY_PROFILE_ACTION to indicate action in memory allocation
lib and user defined action.
4. Extend memory profile protocol to include GetRecordingState/
SetRecordingState/Record.
5. Define SMM memory profile protocol.
6. Extend PcdMemoryProfilePropertyMask to support disable recording at
the start.
7. Introduce new PCD PcdMemoryProfileDriverPath to control which drivers
need memory profile data.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
PI specification Vol 4 - SMM does not have any limitation of BASE_4GB for SMM.
So we should replace BASE_4GB check with MAX_ADDRESS check to make sure
the SMM memory is accessible by SMM Core.
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
GCC build failure: 'RealCommSize' may be used uninitialized
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
According to spec if the length of a descriptor is smaller than
what the specification defines, then the host shall ignore it.
However if the size is greater than expected the host will ignore
the extra bytes and start looking for the next descriptor
at the end of actual length returned. Original check did not
handle the latter case correctly and only allowed descriptors
with lengths exactly as defined in specification.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evgeny Yakovlev <insoreiges@gmail.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Let data of DXE memory status code can be used by other modules.
1. Save the address of DXE memory status code table to DxeConfigurationTable.
2. Save the address of SMM memory status code table to SmmConfigurationTable.
3. Move RUNTIME_MEMORY_STATUSCODE_HEADER to its public header file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Cinnamon Shia <cinnamon.shia@hpe.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The 'Sting' is returned by the function GetUnicodeStringTextAndSize.
If it is NULL, function GetUnicodeStringTextAndSize will return
EFI_OUT_OF_RESOURCES, and error handling codes will cover it.
So the pointer 'Sting' can not be NULL when using it.
So we can add the ASSERT codes.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Use real nasm instruction to replace DB bytes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/S3Asm.asm to X64/S3Asm.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Use real nasm instruction to replace DB bytes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
IA32/S3Asm.asm to IA32/S3Asm.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/EbcLowLevel.asm to X64/EbcLowLevel.nasm
And, manually update nasm code to use mov rcx, dword value and generate
the same assembly code with rcx register to asm code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/EbcLowLevel.asm to Ia32/EbcLowLevel.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/AsmFuncs.asm to X64/AsmFuncs.nasm
Note: Also applied many manual cleanups where conversion script failed
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/AsmFuncs.asm to Ia32/AsmFuncs.nasm
Note: Also applied many manual cleanups where conversion script failed
And, update Vect2Desc() to be same to original logic
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/PageFaultHandler.asm to X64/PageFaultHandler.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/IdtVectorAsm.asm to Ia32/IdtVectorAsm.nasm
Note: Manually updated code storing @VectorTemplateBase address
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Without this change, after converting this code to NASM, this error
will be reported:
error: comma or end of line expected
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
NASM doesn't support EXTERNDEF, so convert this to PUBLIC.
This will make it easier to convert this code to NASM using an
automated script.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Without this change, after converting this code to NASM, this error
will be reported:
error: invalid combination of opcode and operands
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
When a driver also uses a same name, there will be a link error:
one or more multiply defined symbols found.
Use a specific name for mSmst to avoid the link error.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
After booting a large-size ISO RAM disk (HTTP boot option pointing to
a ISO file) and reboot system, system will possibly run into the
following ASSERT because the BDS core code doesn't consider the
case that Memory page management (Page.c) would possibly NOT update
current memory usage statistics(CurrentMemoryTypeInformation) if
system allocates a memory buffer with a large number of pages.
ASSERT [DxeCore] u:\MdeModulePkg\Core\Dxe\Gcd\Gcd.c(2273):
Length >= MinimalMemorySizeNeeded
The BDS code block for skipping counting reserved memory occupied
by RAM Disk didn't consider the Memory page management's behavior
mentioned above, which caused that the
CurrentMemoryTypeInformation[Index1].NumberOfPages will be updated
to a "very big value" because RamDiskSizeInPages is bigger than
CurrentMemoryTypeInformation[Index1].NumberOfPages. For example,
NumberOfPages is 0x9000 (current use) and RamDiskSizeInPages is
0xC0000 (ISO image size). The result will become a very big value
0xFFF49000.
Therefore, we need to add a check to prevent BDS core code updating
wrong data (very big value) to MemoryTypeInformation variable. This
code change is a improvement for fixing this issue for most cases.
There is still a corner case even when the memory bins don't include
the RAM disk memory, the memory used by all other modules exceeds
RamDiskSizeInPages. Ray will send the other patch to fix this corner
case.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sunny Wang <sunnywang@hpe.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This delay is necessary for eMMC reset to working properly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joe Zhou <shjzhou@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
PeiCore EntryPoint library _ModuleEntryPoint() will call PeiCore(), then call
CpuDeadLoop (). When NORETURN is added for PeiCore(), MSVC compiler will report
warning C4702: unreachable code for CpuDeadLoop (). And, the warning is treated
as error and cause build break. DxeMain() has the similar issue.
edk2 uses EntryPoint library to wrap every module entry point function except
for SEC. The module entry point is still called by _ModuleEntryPoint(). So,
there will be negative impact to add NORETURN for the module entry point.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
This patch is used to fix the wrong IpSb->State update issue.
Issue reproduce steps:
1 .First PXE boot, then boot to shell;
2. ifconfig -s eth0 dhcp (Success);
3. Reboot and do PXE, then boot to shell;
4. ifconfig -s eth0 dhcp (Platform failed to get IP address no matter
how many times retried.)
Root cause:
On step3 reboot, policy is DHCP (Changed by step2). So, Ip4Dxe driver
will try to get one IP address from DHCP server automatically. Before
it get the IP address successfully, the IpSb->State will be always in
IP4_SERVICE_STARTED status until the Instance->Dhcp4Event is triggered,
then it can be changed to IP4_SERVICE_CONFIGED. But the DHCP process
will be interrupted by PXE boot, which will change the policy to static,
and the Instance->Dhcp4Event will be also closed directly. However,
current implementation doesn't update the IpSb->State to
IP4_SERVICE_UNSTARTED status in such case. So, failure happened.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Per UEFI spec the successful returning of boot option triggers boot
to UI. But when the BootNext just points to UI, it causes confusing.
So the patch avoids booting to UI again when the BootNext points to
UI.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>
Add a new head file Dhcp.h in Mde/Include/IndustryStandard, normalize the
universal option numbers and other network number tags.
Cc: Sriram Subramanian <sriram-s@hpe.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
It is enough to set PxCMD.FRE bit, which cause HBA to post received FISes
into the FIS receive area. According to AHCI Specification, only polling on
PxCMD.FRE to be cleared is necessary, when it is needeed to stop FIS engine
(eg. in order to change PxCMD.FB address).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Per UEFI spec the successful returning of boot option triggers boot
to UI. But when the BootNext just points to UI, it causes confusing.
So the patch avoids booting to UI again when the BootNext points to
UI.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
This patch adds the NORETURN attribute to functions that transfer to
other phases, along with an UNREACHABLE() call at the end to avoid
false warnings.
DxeIpl has been excluded as its main function returns a status.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Hao Wu
Feng Tian
Star Zeng
Jiewen Yao
Evgeny Yakovlev
Cinnamon Shia
Dandan Bi
Liming Gao
Jordan Justen
Gary Lin
Sunny Wang
Joe Zhou
Jiaxin Wu
Ruiyu Ni
Zhang Lubo
Jan D?bro?
Marvin H?user