Multi-processor PPI header file 'Ppi/Mpservices.h' uses a function
prototype EFI_AP_PROCEDURE which is defined in 'Pi/PiDxeCis.h' (DXE header
file).
This will cause a build fail when 'Ppi/Mpservices.h' is included in a PEI
module.
Since both phase support multi-processor service now, function prototype
EFI_AP_PROCEDURE should be moved to 'Pi/PiMultiPhase.h'. The move is a
compatible change and will not affect other codes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17450 6f19259b-4bc3-4df7-8a09-765794883524
Remove the unused DevicePathSize variable from EnumerateAllKeywords().
Due to our use of -Werror=unused-but-set-variable when building under GCC, the presence of DevicePathSize is breaking the build.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17448 6f19259b-4bc3-4df7-8a09-765794883524
When PcdTpmInstanceGuid is configured to other value,
it means other TPM 2.0 device.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17446 6f19259b-4bc3-4df7-8a09-765794883524
SVN r17428 ("MdeModulePkg: Implement UEFI25 HII Config keyword handler protocol") introduced code that triggers
-Werror=pointer-sign
under gcc ("warn for pointer argument passing or assignment with different signedness"). This patch fix up those locations.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17445 6f19259b-4bc3-4df7-8a09-765794883524
... since gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut has recently
been introduced.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17443 6f19259b-4bc3-4df7-8a09-765794883524
If the device trees are not present when loading FdtPLatformDxe
driver then we should prevent to install the EFI Shell FDT commands.
The EFI Shell commands could be used later to install the missing
device tree.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17441 6f19259b-4bc3-4df7-8a09-765794883524
We need to use msr instruction to write system register. It seems the
code was simply copied from ArmReadCntkCtl.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17440 6f19259b-4bc3-4df7-8a09-765794883524
SVN r15305 (git 5a217a06), "OvmfPkg: S3 Suspend: save boot script after
ACPI context", made this driver install gEfiDxeSmmReadyToLockProtocolGuid
in SaveS3BootScript() -- for valid reasons --, however in the INF file the
protocol was marked as "ALWAYS_CONSUMED". Fix it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17437 6f19259b-4bc3-4df7-8a09-765794883524
The PMBA_RTE and ACPI_TIMER_OFFSET macros apply equally to both boards,
plus they are triplicated between the various AcpiTimerLib instances.
Define them centrally in "OvmfPlatforms.h".
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17436 6f19259b-4bc3-4df7-8a09-765794883524
All POWER_MGMT_REGISTER_PIIX4() macro invocations in OvmfPkg should use
the macros in "I440FxPiix4.h" as arguments.
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17435 6f19259b-4bc3-4df7-8a09-765794883524
All POWER_MGMT_REGISTER_Q35() macro invocations in OvmfPkg should use the
macros in "Q35MchIch9.h" as arguments.
Cc: Gabriel Somlo <somlo@cmu.edu>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17434 6f19259b-4bc3-4df7-8a09-765794883524
Define some new macros for register addresses (both PCI and IO) and
register values (bits) that we're going to use soon.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Gabriel Somlo <somlo@cmu.edu>
Tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17433 6f19259b-4bc3-4df7-8a09-765794883524
Move platform specific macros to their own include files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17432 6f19259b-4bc3-4df7-8a09-765794883524
It provides a repository to cache ESRT info for FMP or Non-FMP instance.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Gao Liming <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17426 6f19259b-4bc3-4df7-8a09-765794883524
When the ExecuteSmmCoreFromSmram() function fails, SmmIplEntry()
restores the SMRAM range to EFI_MEMORY_UC. However, it saves the
return value of gDS->SetMemorySpaceAttributes() in the same Status
variable that gDS->contains the return value of ExecuteSmmCoreFromSmram().
Therefore, if gDS->SetMemorySpaceAttributes() succeeds, the failure
of ExecuteSmmCoreFromSmram() is masked, and Bad Things Happen (TM).
Introduce a temporary variable just for the return value of
gDS->SetMemorySpaceAttributes().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17417 6f19259b-4bc3-4df7-8a09-765794883524
PCI support is only present on Juno R1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17415 6f19259b-4bc3-4df7-8a09-765794883524
Note: This is the same SATA controller present on Juno R1.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17413 6f19259b-4bc3-4df7-8a09-765794883524
Since there is now a formal definition of EFI_LOAD_OPTION, we can no
longer typedef it as a UINT8*. So update the code to use the common
definition, which is not a pointer type, hence the additional changes
to the C code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17410 6f19259b-4bc3-4df7-8a09-765794883524
Current CorebootPayloadPkg uses PciHostBridge and PciBusNoEnumeration
driver. It will cause the PCI bus resource incorrectly set in root
bridge instance. As a result all PCI devices behind a PCI bridge will
not show up in Shell 'PCI' command.
To resolve it use PciRootBridgeNoEnumeration driver instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17408 6f19259b-4bc3-4df7-8a09-765794883524
Update SecureBootConfigDxe component to allow the enrollment of
the digests of EFI executable that are built for ARM or AARCH64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17406 6f19259b-4bc3-4df7-8a09-765794883524
PK can be cleared in runtime. However SecureBootMode variable is not updated accordingly. Add code in variable init to make them consistent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17401 6f19259b-4bc3-4df7-8a09-765794883524
Hao Wu
Eric Dong
Ard Biesheuvel
Samer El-Haj-Mahmoud
Liming Gao
Laszlo Ersek
Ruiyu Ni
Olivier Martin
Heyi Guo
Feng Tian
Chao Zhang
Star Zeng
Shifei Lu
Bob Feng
Maurice Ma