Move these states from the DSDT to the SSDT. Override the default
configuration if the host has the following qemu commit:
commit 459ae5ea5ad682c2b3220beb244d4102c1a4e332
Author: Gleb Natapov <gleb@redhat.com>
Date: Mon Jun 4 14:31:55 2012 +0300
Add PIIX4 properties to control PM system states.
This patch adds two things. First it allows QEMU to distinguish
between regular powerdown and S4 powerdown. Later separate QMP
notification will be added for S4 powerdown. Second it allows
S3/S4 states to be disabled from QEMU command line. Some guests
known to be broken with regards to power management, but allow to
use it anyway. Using new properties management will be able to
disable S3/S4 for such guests.
Supported system state are passed to a firmware using new fw_cfg
file. The file contains 6 byte array. Each byte represents one
system state. If byte at offset X has its MSB set it means that
system state X is supported and to enter it guest should use the
value from lowest 3 bits.
Signed-off-by: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14003 6f19259b-4bc3-4df7-8a09-765794883524
The ACPI 5.0 specification says:
7.3.4.4 System \_S3 State
[...]
* Dynamic RAM context is maintained.
[...]
This corresponds to the following in the PIIX4 spec:
PMCNTRL -- POWER MANAGEMENT CONTROL REGISTER (IO)
[...]
Bits[12:10] Suspend Type
[...]
001 STR (Suspend To RAM)
Also, this (ie. decimal 1) is the suspend type value that qemu recognizes
as an S3 (suspend to ram) request.
Only the value for PM1a_CNT.SLP_TYP is set (PM1b_CNT.SLP_TYP is left at
zero), since in OVMF we don't report the optional PM1b_EVT_BLK register
block to OSPM. (PM1b_EVT_BLK is defined as 0 in "Platform.h"; see "4.8.1.1
PM1 Event Registers" in the ACPI 5.0 specification.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14002 6f19259b-4bc3-4df7-8a09-765794883524
The ACPI 5.0 specification says:
7.3.4.5 System \_S4 State
[...]
* DRAM context is not maintained.
[...]
This corresponds to the following in the PIIX4 spec:
PMCNTRL -- POWER MANAGEMENT CONTROL REGISTER (IO)
[...]
Bits[12:10] Suspend Type
[...]
010 POSCL (Powered On Suspend, Context Lost)
Also, this (ie. decimal 2) is the default suspend type value that qemu
recognizes as an S4 (suspend to disk) request.
Only the value for PM1a_CNT.SLP_TYP is corrected (PM1b_CNT.SLP_TYP is left
at zero), since in OVMF we don't report the optional PM1b_EVT_BLK register
block to OSPM. (PM1b_EVT_BLK is defined as 0 in "Platform.h"; see "4.8.1.1
PM1 Event Registers" in the ACPI 5.0 specification.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14001 6f19259b-4bc3-4df7-8a09-765794883524
Rotate links over devices and pins so that they match qemu.
PIIX4 function 3 (Power Management Module) unconditionally uses the INTA
interrupt pin. SCI from this module requires IRQ9.
Keep other assignments off IRQ9. Only IRQ5, IRQ10, IRQ11 remain for PCI
devices.
Bump OEMRevision in the DSDT.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13625 6f19259b-4bc3-4df7-8a09-765794883524
Kill PDIS and PSRS as they are writing to copies of PIR[A-D], not PIR[A-D]
themselves. Use specialized _DIS and _SRS methods that access PIR[A-D]
directly.
(This should be solvable by passing RefOf (PIRA) etc to PDIS/PSRS, however
the RHEL-6.3 kernel AML parser seems to choke on it. The rules described
in ACPIspec5.0 Table 19-316 "Object Storing and Copying Rules" don't seem
to work:
ACPI Error: Needed [Integer/String/Buffer], found [Reference]
ffff88003ee02420 (20090903/exresop-422)
ACPI Exception: AE_AML_OPERAND_TYPE, While resolving operands for
[OpcodeName unavailable] (20090903/dswexec-445)
ACPI Error (psparse-0537): Method parse/execution failed
[\_SB_.PCI0.LPC_.PDIS] (Node ffff88003f638b50), AE_AML_OPERAND_TYPE
ACPI Error (psparse-0537): Method parse/execution failed
[\_SB_.PCI0.LPC_.LNKA._DIS] (Node ffff88003f638a10),
AE_AML_OPERAND_TYPE
When changing the method too, so that it writes to DerefOf (Arg0) instead
of Arg0, ie. explicitly dereferencing rather than expecting the auto-deref
to work:
ACPI Error: Needed type [Reference], found [RegionField]
ffff88003f639858 (20090903/exresop-104)
ACPI Exception: AE_AML_OPERAND_TYPE, While resolving operands for
[OpcodeName unavailable] (20090903/dswexec-445)
ACPI Error (psparse-0537): Method parse/execution failed
[\_SB_.PCI0.LPC_.PDIS] (Node ffff88003f638b50), AE_AML_OPERAND_TYPE
ACPI Error (psparse-0537): Method parse/execution failed
[\_SB_.PCI0.LPC_.LNKA._DIS] (Node ffff88003f638a10),
AE_AML_OPERAND_TYPE
In short, when passing a RefOf, it is recognized as a reference inside the
method but mistakenly refused. When trying to deref it explicitly with
DerefOf, then it's suddenly not recognized as a reference.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13621 6f19259b-4bc3-4df7-8a09-765794883524
0xb000 is the address normally used with QEMU.
0x400 also appears to conflict with some debug I/O ports
used by QEMU.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13279 6f19259b-4bc3-4df7-8a09-765794883524
QEMU hard codes the GPE0 registers at 0xafe0.
Previously the code assumed that the GPE0 block
would move when the PM Base Address of the PIIX4
PCI device was programmed. It appears QEMU does not
emulate this behaviour of the PIIX4 PCI device.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Bei Guan <gbtju85@gmail.com>
Reviewed-by: Bei Guan <gbtju85@gmail.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13276 6f19259b-4bc3-4df7-8a09-765794883524
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