Commit Graph

1087 Commits

Author SHA1 Message Date
Ray Ni fe3ca5fd25 UefiCpuPkg/MpInitLib: Remove global variable X2ApicEnable
MpInitLib sets X2ApicEnable in two places.
1. CollectProcessorCount()
   This function is called when MpInitLibInitialize() hasn't been
   called before.
   It sets X2ApicEnable and later in the same function it configures
   all CPUs to operate in X2 APIC mode.
2. MpInitLibInitialize()
   The X2ApicEnable setting happens when this function is called in
   second time. But after that setting, no code consumes that flag.

With the above analysis and with the purpose of simplifying the code,
the X2ApicEnable in #1 is changed to local variable and the #2 can be
changed to remove the setting of X2ApicEnable.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-11-05 10:03:44 +08:00
Ray Ni 54d1e76f4e UefiCpuPkg/MpInitLib: Set X2ApicEnable flag from BSP
Today's logic sets X2ApicEnable flag in each AP's initialization
path when InitFlag == ApInitConfig.
Since all CPUs update the same global data, a spin-lock is used
to avoid modifications from multiple CPUs happen at the same time.
The spin-lock causes two problems:
1. Potential performance downgrade.
2. Undefined behavior when improper timer lib is used.
   For example we saw certain platforms used AcpiTimerLib from
   PcAtChipsetPkg and that library depends on retrieving PeiServices
   from idtr. But in fact AP's (idtr - 4) doesn't point to
   PeiServices.

The patch simplifies the code to let BSP set the X2ApicEnable flag so
the spin-lock acquisition from AP is not needed any more.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-11-05 10:03:43 +08:00
Sean Brogan 20c082e8d7 UefiCpuPkg: Add missing components to UefiCpuPkg.dsc
https://bugzilla.tianocore.org/show_bug.cgi?id=2255

Update UefiCpuPkg.dsc to guarantee all libraries and
modules are always built.  Add the following components.

* UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf
* UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf

ResetVector.inf is a binary INF, so no source builds are
triggered from adding this line.  However, a build with
this component does verify the contents of the INF file.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-10-23 17:47:29 -07:00
Laszlo Ersek 778832bcad UefiCpuPkg/MpInitLib: honor the platform's boot CPU count in AP detection
- If a platform boots such that the boot CPU count is smaller than
  PcdCpuMaxLogicalProcessorNumber, then the platform cannot use the "fast
  AP detection" logic added in commit 6e1987f19a. (Which has been
  documented as a subset of use case (2) in the previous patch.)

  Said logic depends on the boot CPU count being equal to
  PcdCpuMaxLogicalProcessorNumber. If the equality does not hold, the
  platform either has to wait too long, or risk missing APs due to an
  early timeout.

- The platform may not be able to use the variant added in commit
  0594ec417c either. (Which has been documented as use case (1) in the
  previous patch.)

  See commit 861218740d. When OVMF runs on QEMU/KVM, APs may check in
  with the BSP in arbitrary order, plus the individual AP may take
  arbitrarily long to check-in. If "NumApsExecuting" falls to zero
  mid-enumeration, APs will be missed.

Allow platforms to specify the exact boot CPU count, independently of
PcdCpuMaxLogicalProcessorNumber. In this mode, the BSP waits for all APs
to check-in regardless of timeout. If at least one AP fails to check-in,
then the AP enumeration hangs forever. That is the desired behavior when
the exact boot CPU count is known in advance. (A hung boot is better than
an AP checking-in after timeout, and executing code from released
storage.)

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1515
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-10-11 23:20:09 +02:00
Laszlo Ersek 30459ddde6 UefiCpuPkg/MpInitLib: expand comment on initial AP enumeration
Before adding another AP enumeration mode, clarify the documentation on
the current logic. No functional changes.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1515
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-10-11 23:19:41 +02:00
Leif Lindholm d19040804a UefiCpuPkg: strip trailing whitespace
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
2019-10-04 11:18:32 +01:00
Dong, Eric c70fef962e UefiCpuPkg/CpuDxe: clean up PAGE_TABLE_LIB_PAGING_CONTEXT usage.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1039

Current implementation not checks system mode before using
PAGE_TABLE_LIB_PAGING_CONTEXT.ContextData.X64 or
PAGE_TABLE_LIB_PAGING_CONTEXT.ContextData.Ia32. This patch check the
mode before using the correct one.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-25 14:29:24 +08:00
John E Lofgren f4c898f2b2 UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150

v4:
The v3 posting didn't do what it promised to do, so do it now for real.

V3 changes:
change to mov instruction (non locking instuction) instead
of xchg to simplify design.

V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used

Split lock happens when a locking instruction is used on mis-aligned data
that crosses two cachelines. If close source platform enables Alignment
Check Exception(#AC), They can hit a double fault due to split lock being
in CpuExceptionHandlerLib.

sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
The data is mis-aligned, can cross two cacheline, and a xchg
instruction(locking instuction) is being utilize.

Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-20 14:37:42 +08:00
Damian Nikodem 832c4c7ad6 UefiCpuPkg: Fix potential spinLock issue in SmmStartupThisAp
Due to needs a tackling the deficiency of the AP API, it's necessary to
ensure that in non-blocking mode previous AP executed command is
finished before starting new one.

To remedy above:
  1) execute AcquireSpinLock instead AcquireSpinLockOrFail - this will
     ensure time "window" to eliminate potential race condition between
     BSP and AP spinLock release in non-blocking mode.
     This also will eliminate possibility to start executing new AP
     function before last is finished.
  2) remove returns EFI_STATUS - EFI_NOT_READY - in new scenario returned
     status is not necessary to caller.

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Krzysztof Rusocki <krzysztof.rusocki@intel.com>
2019-09-20 14:37:42 +08:00
Ray Ni 136dad0956 UefiCpuPkg: Remove PcdCpuSmmStaticPageTable
PcdCpuSmmRestrictedMemoryAccess is introduced to replace
PcdCpuSmmStaticPageTable.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-19 14:25:24 +08:00
Ray Ni 86ad762fa7 UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48
Today's behavior is to enable 5l paging when CPU supports it
(CPUID[7,0].ECX.BIT[16] is set).

The patch changes the behavior to enable 5l paging when two
conditions are both met:
1. CPU supports it;
2. The max physical address bits is bigger than 48.

Because 4-level paging can support to address physical address up to
2^48 - 1, there is no need to enable 5-level paging with max
physical address bits <= 48.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
2019-09-13 16:20:54 +08:00
Chasel Chiu 8a1305a11f UefiCpuPkg: support single EFI_PEI_CORE_FV_LOCATION_PPI in PpiList
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2153

Current logic will skip searching EFI_PEI_CORE_FV_LOCATION_PPI when the
PPI in PpiList having EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST flag,
but platform may pass single PPI in PpiList that should be supported.

Changed the logic to verify PpiList first before checking
EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST flag.

Test: Verified both single EFI_PEI_CORE_FV_LOCATION_PPI and multiple
      PPIs in PpiList cases and both can boot with the PeiCore
      specified by EFI_PEI_CORE_FV_LOCATION_PPI.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-09-05 20:42:20 +08:00
Ray Ni f64a597d45 UefiCpuPkg: Explain relationship between several SMM PCDs
There are three PCDs that may impact the behavior of each other in
SMM environment:
  PcdCpuSmmProfileEnable
  PcdHeapGuardPropertyMask in MdeModulePkg
  PcdCpuSmmRestrictedMemoryAccess

The patch updates the comments in DEC file to document it.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-04 01:00:11 +08:00
Ray Ni 79186ddcdd UefiCpuPkg/PiSmmCpu: Restrict access per PcdCpuSmmRestrictedMemoryAccess
Today's behavior is to always restrict access to non-SMRAM regardless
the value of PcdCpuSmmRestrictedMemoryAccess.

Because RAS components require to access all non-SMRAM memory, the
patch changes the code logic to honor PcdCpuSmmRestrictedMemoryAccess
so that only when the PCD is true, the restriction takes affect and
page table memory is also protected.

Because IA32 build doesn't reference this PCD, such restriction
always takes affect in IA32 build.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-04 01:00:10 +08:00
Ray Ni 09f7c82b4c UefiCpuPkg/PiSmmCpu: Use new PCD PcdCpuSmmRestrictedMemoryAccess
The patch changes PiSmmCpu driver to consume PCD
PcdCpuSmmRestrictedMemoryAccess.
Because the behavior controlled by PcdCpuSmmStaticPageTable in
original code is not changed after switching to
PcdCpuSmmRestrictedMemoryAccess.

The functionality is not impacted by this patch.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-04 01:00:10 +08:00
Ray Ni 87184487d2 UefiCpuPkg: Add PcdCpuSmmRestrictedMemoryAccess
The patch adds a new X64 only PCD PcdCpuSmmRestrictedMemoryAccess.
The PCD indicates access to non-SMRAM memory is restricted to
reserved, runtime and ACPI NVS type after SmmReadyToLock.
MMIO access is always allowed regardless of the value of this PCD.
Loose of such restriction is only required by RAS components in X64
platforms.
The PCD value is considered as constantly TRUE in IA32 platforms.
When the PCD value is TRUE, page table is initialized to cover all
memory spaces and the memory occupied by page table is protected by
page table itself as read-only.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-09-04 01:00:10 +08:00
Eric Dong 47f167f47e UefiCpuPkg/SecCore: get AllSecPpiList after SecPlatformMain.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2136

SecPlatformMain is a platform hook function which let platform does
some update. Some platform may adjust SecCoreData->PeiTemporaryRamBase
which caused former saved AllSecPpiList variable invalid.

This patch update the logic to get AllSecPpiList after SecPlatformMain.
If SecPlatformMain() returns no platform-specific PPI list, then there
is nothing to merge, so we don't need "AllSecPpiList" at all.

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-30 21:49:49 +08:00
Donald Kuo 30781febe2 UefiCpuPkg: Adding a new TSC library by using CPUID(0x15) TSC leaf
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1909

Cc: Ray Ni <ray.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Donald Kuo <donald.kuo@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-21 21:36:56 +08:00
Dong, Eric 9c90d39b60 UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Below code is current implementation:
  if (MsrRegister[ProcessorNumber].Bits.Lock == 0) {
    CPU_REGISTER_TABLE_WRITE_FIELD (
      ProcessorNumber,
      Msr,
      MSR_IA32_FEATURE_CONTROL,
      MSR_IA32_FEATURE_CONTROL_REGISTER,
      Bits.Lock,
      1
    );
  }

1. In first normal boot, the Bits.Lock is 0, 1 will be added
   into the register table and then will set to the MSR.
2. Trig warm reboot, MSR value preserves. After normal boot phase,
   the Bits.Lock is 1, so it will not be added into the register
   table during the warm reboot phase.
3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is
   not added in register table, so it's still 0 after resume. This
   is not an expect behavior. The expect value is the value should
   always 1 after booting or resuming from S3.

The root cause for this issue is
1. driver bases on current value to insert the "set value action" to
   the register table.
2. Some MSRs may reserve their value during warm reboot.

The solution for this issue is using new added macros for the MSRs which
preserve value during warm reboot.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21 02:44:50 +08:00
Dong, Eric 95cfe6c247 UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Supports new logic which test current value before write new value.
Only write new value when current value not same as new value.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21 02:44:49 +08:00
Dong, Eric 6b3645ade5 UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21 02:44:49 +08:00
Dong, Eric cfbcaad251 UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Supports new logic which test current value before write new value.
Only write new value when current value not same as new value.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21 02:44:49 +08:00
Dong, Eric ef21a304e0 UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-21 02:44:48 +08:00
Dong, Eric 35c2809ba6 UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040

Add below new micros which test the current value before write the new
value. Only write new value when current value not same as new value.
  CPU_REGISTER_TABLE_TEST_THEN_WRITE32
  CPU_REGISTER_TABLE_TEST_THEN_WRITE64
  CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD

Also add below API:
  CpuRegisterTableTestThenWrite

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Cc: Star Zeng <star.zeng@intel.com>
2019-08-21 02:44:48 +08:00
Damian Nikodem 4201098e97 UefiCpuPkg/PiSmmCpuDxeSmm: don't free page table pages that are required to handle current page fault
Reclaim may free page table pages that are required to handle current page
fault. This causes a page leak, and, after sufficent number of specific
page fault+reclaim pairs, we run out of reclaimable pages and hit:

ASSERT (MinAcc != (UINT64)-1);

To remedy, prevent pages essential to handling current page fault:
(1) from being considered as reclaim candidates (first reclaim phase)
(2) from being freed as part of "branch cleanup" (second reclaim phase)

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Jian J Wang <jian.j.wang@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Krzysztof Rusocki <krzysztof.rusocki@intel.com>
2019-08-21 02:44:48 +08:00
Shenglei Zhang 501de8146d UefiCpuPkg/Cpuid: Add description for parameter LeafFunction
LeafFunction needs to be described in comments.
https://bugzilla.tianocore.org/show_bug.cgi?id=2052

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-16 14:01:49 +08:00
Shenglei Zhang 073f2cede8 UefiCpuPkg/PiSmmCpuDxeSmm: Fix coding style
1. Update CPUStatus to CpuStatus in comments to align comments
   with code.
2. Add "OUT" attribute for "ProcedureArguments" parameter in function
   header.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-13 17:20:32 +08:00
Eric Dong 466f5e89c3 UefiCpuPkg/PiSmmCpuDxeSmm: Clean up useless ConsoleLogLock spinlock.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2060

Remove the useless ConsoleLogLock spinlock.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-09 08:55:57 +08:00
Eric Dong 800aeeda74 UefiCpuPkg/RegisterCpuFeaturesLib: Clean up useless ConsoleLogLock spinlock.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2060

Remove the useless ConsoleLogLock spinlock.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-09 08:55:57 +08:00
Ni, Ray 01acb06c4f UefiCpuPkg: Update code to include register definitions from MdePkg
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09 08:52:09 +08:00
Ni, Ray e057908f8d UefiCpuPkg|MdePkg: Move Register/ folder to MdePkg/Include/
The patch moves all files under UefiCpuPkg/Include/Register/ to
MdePkg/Include/Register using following detailed approaches:
1. Move UefiCpuPkg/Include/Register/Amd/ to
   MdePkg/Include/Register/Amd folder.
2. Move remaining in UefiCpuPkg/Include/Register/ to
   MdePkg/Include/Register/Intel folder.
3. Create wrapper header files under UefiCpuPkg/Include/Register/
   to include the accordingly files in MdePkg/Include/Register/Intel.
   This is to avoid build break because code in other repos like
   edk2-platform includes the file from UefiCpuPkg.

The wrapper header files will be removed after all consumers code
is updated.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09 08:52:09 +08:00
Ni, Ray 236d5c66c4 MdePkg/Cpuid.h: Move Cpuid.h from UefiCpuPkg to MdePkg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008

MdeModulePkg/DxeIpl needs to get CPUID output for CPU
5-level paging capability detection.

In order to use the macros/structures defined in
UefiCpuPkg/Include/Register/Cpuid.h, the patch adds Intel/Cpuid.h
to MdePkg/Include/Register/ directory and updates Cpuid.h
in UefiCpuPkg to include the new one in MdePkg.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09 08:52:08 +08:00
Ni, Ray e58aa47432 UefiCpuPkg/CpuDxe: Support parsing 5-level page table
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09 08:52:08 +08:00
Ni, Ray 29355b4e1a UefiCpuPkg/CpuDxe: Remove unnecessary macros
Today's code defines macros like CR0_PG, CR0_WP, CR4_PSE, CR4_PAE
when checking whether individual bits are set in CR0 or CR4 register.

The patch changes the code to use IA32_CR0 and IA32_CR4 structure
defined in MdePkg/Include/Library/BaseLib.h so that the module
local macros can be removed.

There is no functionality impact to this change.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09 08:52:08 +08:00
Ni, Ray 09f69a877b UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008

MpInitLib is the library that's responsible to wake up APs to provide
MP PPI and Protocol services.

The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57.
Without this change, AP may enter to GP fault when BSP's 5-level page
table is set to AP during AP wakes up.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
2019-08-09 08:52:08 +08:00
Eric Dong 02031cfc92 UefiCpuPkg/PiSmmCpuDxeSmm: Remove debug message.
This debug message may be called by BSP and APs. It may
caused ASSERT when APs call this debug code.

In order to avoid system boot assert, Remove this debug
message.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
2019-08-06 11:29:04 +08:00
Eric Dong 1821dbed1d UefiCpuPkg/RegisterCpuFeaturesLib: Remove debug message.
This debug message may be called by BSP and APs. It may
caused ASSERT when APs call this debug code.

In order to avoid system boot assert, Remove this debug
message.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
2019-08-06 11:28:57 +08:00
shenglei 5ed4c46f11 UefiCpuPkg/PiSmmCpuDxeSmm: Make code consistent with comments
1.Remove "out" attribute for " Buffer" parameter in function header.
2.Add "out" attribute for " Token" parameter in function header.
3.Update ProcedureArgument to ProcedureArguments.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-06 11:28:41 +08:00
Shenglei Zhang aefcf2f78a UefiCpuPkg/PiSmmCpuDxeSmm: Add check for pointer Pml5Entry
The pointer Pml5Entry, returned from call to function
AllocatePageTableMemory, may be null.
So add check for it.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-08-05 16:31:34 +08:00
Eric Dong 89164babec UefiCpuPkg/MpInitLib: don't shadow the microcode patch twice.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1982

MpInitLibInitialize in MpLib.c will be invoked on both PEI and DXE
CPU code, MicrocodeDetect would be performed twice and copy
Microcode from flash to memory twice as well, which consider as
duplicate work to lead longer boot time.
This patch just use microcode memory copied in PEI phase if exist.

Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-02 16:41:19 +08:00
Shenglei Zhang 46e34cc956 UefiCpuPkg/PiSmmCpuDxeSmm: Keep function comment and declaration adjacent
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-08-02 14:19:13 +08:00
Eric Dong 87ad6913b4 UefiCpuPkg/RegisterCpuFeaturesLib: Start all processors simultaneously.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973

For semaphore type register, it required all processors to do the
task at the same time.
Current logic begins BSP's task after all APs have finished their tasks.
This will caused set semaphore task hang if semaphore has package
level type.
This patch use new EDKII_PEI_MP_SERVICES2_PPI to start all processors at
the same time to fix the potential hang issue.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-07-29 09:25:20 +08:00
Eric Dong a430589cb5 UefiCpuPkg/CpuMpPei: Produce EDKII_PEI_MP_SERVICES2_PPI.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973

Produce new EDKII_PEI_MP_SERVICES2_PPI service.

It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI
and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29 09:25:20 +08:00
Eric Dong ebfbb70129 UefiCpuPkg: Add new EDKII_PEI_MP_SERVICES2_PPI
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973

Add definition for new EDKII_PEI_MP_SERVICES2_PPI.

It includes all APIs existed in EFI_PEI_MP_SERVICES_PPI
and add new API EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29 09:25:20 +08:00
Eric Dong c06a657f4f UefiCpuPkg/MpInitLibUp: Add MpInitLibStartupAllCPUs API.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973

Add new MpInitLibStartupAllCPUs API uses to start all processors
at the same time.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-07-29 09:25:20 +08:00
Eric Dong ee0c39fa11 UefiCpuPkg/MpInitLib: Add MpInitLibStartupAllCPUs API.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973

Add new MpInitLibStartupAllCPUs API uses to start all processors
at the same time.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29 09:25:20 +08:00
Eric Dong 92b5a2eabc UefiCpuPkg/Include/MpInitLib.h: Add MpInitLibStartupAllCPUs API.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973

Add new MpInitLibStartupAllCPUs API uses to start all processors
at the same time.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2019-07-29 09:25:19 +08:00
Laszlo Ersek d47b85a621 Revert "UefiCpuPkg/PiSmmCpu: Allow SMM access-out when static paging is OFF"
This reverts commit 30f6148546.

Commit 30f6148546 causes a build failure, when building for IA32:

> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c: In function
> 'PerformRemainingTasks':
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c:1440:9: error:
> 'mCpuSmmStaticPageTable' undeclared (first use in this function)
>      if (mCpuSmmStaticPageTable) {

"mCpuSmmStaticPageTable" is an X64-only variable. It is defined in
"X64/PageTbl.c", which is not linked into the IA32 binary. We must not
reference the variable in such code that is linked into both IA32 and X64
builds, such as "PiSmmCpuDxeSmm.c".

We have encountered the same challenge at least once in the past:

- https://bugzilla.tianocore.org/show_bug.cgi?id=1593
- commit 37f9fea5b8 ("UefiCpuPkg\CpuSmm: Save & restore CR2 on-demand
  paging in SMM", 2019-04-04)

The right approach is to declare a new function in "PiSmmCpuDxeSmm.h", and
to provide two definitions for the function, one in "Ia32/PageTbl.c", and
another in "X64/PageTbl.c". The IA32 implementation should return a
constant value. The X64 implementation should return
"mCpuSmmStaticPageTable". (In the example named above, the functions were
SaveCr2() and RestoreCr2().)

Signed-off-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: push revert immediately, due to build breakage that
 would have been easy to catch before submitting the patch]
2019-07-26 11:59:56 +02:00
Ni, Ray 30f6148546 UefiCpuPkg/PiSmmCpu: Allow SMM access-out when static paging is OFF
Commit c60d36b4d1
* UefiCpuPkg/SmmCpu: Block access-out only when static paging is used

updated page fault handler to treat SMM access-out as allowed
address when static paging is not used.

But that commit is not complete because the page table is still
updated in SetUefiMemMapAttributes() for non-SMRAM memory. When SMM
code accesses non-SMRAM memory, page fault is still generated.

This patch skips to update page table for non-SMRAM memory and
page table itself.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-07-26 14:55:47 +08:00
Dong, Eric 3dafa03822 UefiCpuPkg/RegisterCpuFeaturesLib: avoid use dynamic PCD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972

Function in this library may be used by APs. Assert will be trig if AP
uses dynamic pcd.
This patch enhance the current code, remove the unnecessary usage of
dynamic PCD. This change try to avoid report this issue again later.

Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Chandana Kumar <chandana.c.kumar@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2019-07-18 08:22:19 +08:00