Olivier Martin 48ef4e4276 ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level ... If the first entry of the memory map is in the third level (case when the region at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3 (=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3). The first condition in GetFirstPageAttribute() needed the table level to not mix these two descriptor types. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524		2014-05-14 05:32:07 +00:00
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AArch64	ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level	2014-05-14 05:32:07 +00:00
ArmV4	ARM Packages: Fixed line endings	2013-01-25 11:28:06 +00:00
ArmV6	ArmPkg/CpuDxe: Removed LR adjustement for SVC call	2013-11-28 21:38:56 +00:00
CpuDxe.c	ARM Packages: Fixed Build failings/warnings/EDK2 coding convention	2011-09-27 16:42:47 +00:00
CpuDxe.h	ArmPkg/CpuDxe: Added support to not set a memory region with the same attribute	2013-08-19 17:38:39 +00:00
CpuDxe.inf	ARM Packages: Remove GCC filter for AARCH64 assembly files	2014-05-08 14:54:11 +00:00
CpuMmuCommon.c	ArmPkg/CpuDxe: Added support to not set a memory region with the same attribute	2013-08-19 17:38:39 +00:00
CpuMpCore.c	ArmPkg: Create MpCoreInfo PPI and HOB to describe CPU Cores on a MPCore platform	2011-09-22 23:14:01 +00:00