Ard Biesheuvel 28f8d28faa ArmPkg/ArmGicLib: manage GICv3 SPI state at the distributor
Unlike SGIs and PPIs, which are private to the CPU and are managed at
the redistributor level (which is also a per-CPU construct), shared
interrupts (SPIs) are shared between all CPUs, and therefore managed at
the distributor level (just as on GICv2).

Reported-by: Narinder Dhillon <ndhillonv2@gmail.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-07-13 16:37:21 +02:00
2014-10-14 16:08:15 +00:00
2016-04-22 00:55:21 -07:00
2016-07-11 10:29:45 +08:00
2016-07-13 08:39:50 +02:00
2014-10-14 16:08:15 +00:00
Description
Acidanthera UEFI Development Kit based on EDK II edk2-stable202405
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