Duggapu Chinni B 543add1d41 IntelFsp2Pkg: Fsp T new ARCH UPD Support ... Changes to support spec changes 1. Remove usage of Pcd. 2. Change code to validate the Temporary Ram size input. 3. Consume the input saved in YMM Register Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chiu Chasel <chasel.chiu@intel.com> Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com> Cc: Ni Ray <ray.ni@intel.com> Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com> Reviewed-by: Chiu Chasel <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>		2024-04-09 17:15:10 +00:00
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Ia32	IntelFsp2Pkg: Fsp T new ARCH UPD Support	2024-04-09 17:15:10 +00:00
Vtf0	IntelFsp2Pkg: Fix various typos	2019-07-11 21:07:17 +08:00
X64	IntelFsp2Pkg: Fsp T new ARCH UPD Support	2024-04-09 17:15:10 +00:00
Fsp22SecCoreS.inf	IntelFsp2Pkg: FspSecCore support for X64	2022-04-16 00:18:14 +00:00
Fsp24SecCoreM.inf	IntelFsp2Pkg: Fsp T new ARCH UPD Support	2024-04-09 17:15:10 +00:00
Fsp24SecCoreS.inf	IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions.	2022-09-07 04:21:15 +00:00
FspSecCoreI.inf	IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support.	2022-07-20 02:15:55 +00:00
FspSecCoreM.inf	IntelFsp2Pkg: Fsp T new ARCH UPD Support	2024-04-09 17:15:10 +00:00
FspSecCoreS.inf	IntelFsp2Pkg: FspSecCore support for X64	2022-04-16 00:18:14 +00:00
FspSecCoreT.inf	IntelFsp2Pkg: FspSecCore support for X64	2022-04-16 00:18:14 +00:00
SecFsp.c	IntelFsp2Pkg: Fsp T new ARCH UPD Support	2024-04-09 17:15:10 +00:00
SecFsp.h	IntelFsp2Pkg: Fsp T new ARCH UPD Support	2024-04-09 17:15:10 +00:00
SecFspApiChk.c	IntelFsp2Pkg: FSP should support input UPD as NULL.	2022-11-04 03:04:51 +00:00
SecMain.c	IntelFsp2Pkg: Update SEC_IDT_TABLE struct	2022-07-14 18:13:44 +00:00
SecMain.h	IntelFsp2Pkg: auto-generate SEC ProcessLibraryConstructorList() decl	2024-03-08 09:09:22 +00:00