Feng Tian db98a8bdb8 MdeModulePkg/XhciDxe: fix a bug on TRB check in async int transfer ...

The last TRB in transfer ring is a LINK type TRB, which shouldn't
be accounted as a valid item in IsAsyncIntTrb().

Without this fix, the original algo will bring issue on those URBs
whose TRBs crosses the transfer ring.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

2016-07-25 09:37:05 +08:00

..

ComponentName.c

1) remove wrong global variable usage because it will bring data corrupt if there are multiple XHCI host controllers.

2011-09-14 12:13:03 +00:00

ComponentName.h

Enabling usb3.0 XHCI support.

2011-08-23 14:36:33 +00:00

UsbHcMem.c

MdeModulePkg: Fix typos in comments and variables

2016-07-11 10:29:48 +08:00

UsbHcMem.h

Update XHCI driver to use PCI IO AllocateBuffer/Map/Unmap to do DMA operation.

2013-08-12 08:51:55 +00:00

Xhci.c

MdeModulePkg/Usb: Fix wrong condition judgment to support usb3.1 dev

2016-04-21 15:53:14 +08:00

Xhci.h

MdeModulePkg/Xhci: make all timeout values be consistent with comments.

2015-08-19 03:41:38 +00:00

XhciDxe.inf

MdeModulePkg: XhciDxe: list ARM and AARCH64 as valid architectures

2015-03-16 19:57:21 +00:00

XhciDxe.uni

MdeModulePkg: Convert all .uni files to utf-8

2015-12-15 04:56:23 +00:00

XhciDxeExtra.uni

MdeModulePkg: Convert all .uni files to utf-8

2015-12-15 04:56:23 +00:00

XhciReg.c

MdeModulePkg/Xhci: make all timeout values be consistent with comments.

2015-08-19 03:41:38 +00:00

XhciReg.h

Update XhcWaitOpRegBit to take Timout argument as microsecond.

2013-12-25 07:52:55 +00:00

XhciSched.c

MdeModulePkg/XhciDxe: fix a bug on TRB check in async int transfer

2016-07-25 09:37:05 +08:00

XhciSched.h

MdeModulePkg/Xhci: Remove TDs from transfer ring when timeout happens

2015-08-26 01:19:09 +00:00