mirror of https://github.com/acidanthera/audk.git
553dfb0f57
OS may enable CET-IBT feature by set MSR IA32_U_CET.bit2. If IA32_U_CET.bit2 is set, CPU is in WAIT_FOR_ENDBRANCH state and the next assemble code is not ENDBR, it will trigger #CP exception when set CR4.CET bit. SMI handler needs to backup MSR IA32_U_CET and clear MSR IA32_U_CET before set CR4.CET bit, And SMI handler needs to restore MSR IA32_U_CET when exit SMI handler. Signed-off-by: Sheng Wei <w.sheng@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Cc: Tan Dun <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> |
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|---|---|---|
| .. | ||
| Cet.nasm | ||
| MpFuncs.nasm | ||
| PageTbl.c | ||
| Semaphore.c | ||
| SmiEntry.nasm | ||
| SmiException.nasm | ||
| SmmFuncsArch.c | ||
| SmmInit.nasm | ||
| SmmProfileArch.c | ||
| SmmProfileArch.h | ||