Jeff Fan 9c71e1e056 1. Save/restore ICR high 32bit value and check Delivery Status before sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler. ... 2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler. 3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com> Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524		2014-07-11 02:36:56 +00:00
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BaseUefiCpuLib	Fix CRLF format	2014-01-22 08:41:16 +00:00
BaseXApicLib	1. Save/restore ICR high 32bit value and check Delivery Status before sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler.	2014-07-11 02:36:56 +00:00
BaseXApicX2ApicLib	1. Save/restore ICR high 32bit value and check Delivery Status before sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler.	2014-07-11 02:36:56 +00:00
CpuExceptionHandlerLib	Fixed typos: hanlder should be handler.	2014-07-09 03:51:56 +00:00
MtrrLib	MtrrDebugPrintAllMtrrs() should loop until the max physical address is reached.	2014-01-07 06:24:16 +00:00
SecPeiDxeTimerLibUefiCpu	Removed the assumption on APIC timer initial Count is all 1s and updated it to handle the long delay that timer initial count.	2013-08-27 07:29:45 +00:00