audk/UefiCpuPkg/PiSmmCpuDxeSmm/X64
Marvin H?user 4222e8e7e4 UefiCpuPkg/PiSmmCpuDxeSmm: Fix ASSERT for success.
Index is initialized to MAX_UINT16 as default failure value, which
is what the ASSERT is supposed to test for.  The ASSERT condition
however can never return FALSE for INT16 != int, as due to
Integer Promotion[1], Index is converted to int, which can never
result in -1.

Furthermore, Index is used as a for loop index variable inbetween its
initialization and the ASSERT, so the value is unconditionally
overwritten too.

Fix the ASSERT check to compare Index to its upper boundary, which it
will be equal to if the loop was not broken out of on success.

[1] ISO/IEC 9899:2011, 6.5.9.4

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2018-10-30 10:21:33 +08:00
..
MpFuncs.nasm UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain 2018-01-16 23:43:08 +08:00
PageTbl.c UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM 2018-08-30 07:22:30 +08:00
Semaphore.c UefiCpuPkg/PiSmmCpuDxeSmm: remove DBs from SmmRelocationSemaphoreComplete32() 2018-04-04 16:44:25 +02:00
SmiEntry.nasm UefiCpuPkg PiSmmCpuDxeSmm: Update SmiEntry function run the same position 2018-09-25 08:25:41 +08:00
SmiException.nasm UefiCpuPkg/PiSmmCpuDxeSmm: use mnemonics for FXSAVE(64)/FXRSTOR(64) 2018-04-04 16:44:27 +02:00
SmmFuncsArch.c UefiCpuPkg/PiSmmCpuDxeSmm: Fix ASSERT for success. 2018-10-30 10:21:33 +08:00
SmmInit.nasm UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM 2018-08-21 16:10:42 +08:00
SmmProfileArch.c UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask 2017-03-01 12:53:03 +08:00
SmmProfileArch.h
StuffRsb.inc UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM 2018-08-21 16:10:42 +08:00