mirror of https://github.com/acidanthera/audk.git
ffdd337630
Section 7.8.2 of the PCI Express specification (r4.0 v0.3), entitled "PCI Express Capabilities Register (Offset 02h)", and section 7.8.9 "Slot Capabilities Register (Offset 14h)" of the same, describe the conditions when a PCIe port should be considered "supporting hotplug": - it should be a root complex port or a switch downstream port, and - it should have the "Slot Implemented" bit set in the Express Capabilities Register, and - it should have the "Hot-Plug Capable" bit set in the Slot Capabilities Register. The first two sub-conditions are already implemented in at least two open source projects I could find: - in SeaBIOS by Marcel Apfelbaum: "hw/pci: reserve IO and mem for pci express downstream ports with no devices attached" <https://code.coreboot.org/p/seabios/source/commit/3aa31d7d6375>, - in edk2 itself, in the implementation of the "PCI" UEFI Shell command: see the "PcieExplainTypeSlot" case label in function PciExplainPciExpress(), file "ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c". PciBusDxe recognizes such PCIe ports as bridges, but it doesn't realize they support hotplug. In turn PciBusDxe omits getting any resource padding information from the platform's EFI_PCI_HOT_PLUG_INIT_PROTOCOL for these bridges: GatherPpbInfo() [PciEnumeratorSupport.c] GetResourcePaddingPpb() [PciResourceSupport.c] GetResourcePaddingForHpb() [PciHotPlugSupport.c] IsPciHotPlugBus() [PciHotPlugSupport.c] // // returns FALSE // // // the following is not reached: // gPciHotPlugInit->GetResourcePadding() Implement a function called SupportsPcieHotplug() for identifying such ports, and call it from IsPciHotPlugBus() (after the call to IsSHPC()). Cc: "Johnson, Brian J." <bjohnson@sgi.com> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com> |
||
|---|---|---|
| .. | ||
| EhciDxe | ||
| EhciPei | ||
| IdeBusPei | ||
| IncompatiblePciDeviceSupportDxe | ||
| NvmExpressDxe | ||
| PciBusDxe | ||
| PciHostBridgeDxe | ||
| PciSioSerialDxe | ||
| SdMmcPciHcDxe | ||
| SdMmcPciHcPei | ||
| UfsPciHcDxe | ||
| UfsPciHcPei | ||
| UhciDxe | ||
| UhciPei | ||
| XhciDxe | ||
| XhciPei | ||