2016-07-20 16:44:39 +02:00
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;------------------------------------------------------------------------------ ;
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2023-03-01 07:09:52 +01:00
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; Copyright (c) 2015 - 2023, Intel Corporation. All rights reserved.<BR>
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2019-04-04 01:07:22 +02:00
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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2016-07-20 16:44:39 +02:00
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;
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; Module Name:
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;
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; MpFuncs.nasm
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;
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; Abstract:
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;
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; This is the assembly code for MP support
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;
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;-------------------------------------------------------------------------------
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%include "MpEqu.inc"
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extern ASM_PFX(InitializeFloatingPointUnits)
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2021-12-09 04:27:30 +01:00
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%macro OneTimeCall 1
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jmp %1
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%1 %+ OneTimerCallReturn:
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%endmacro
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%macro OneTimeCallRet 1
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jmp %1 %+ OneTimerCallReturn
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%endmacro
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2016-07-20 16:44:39 +02:00
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DEFAULT REL
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SECTION .text
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;-------------------------------------------------------------------------------------
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;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
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;procedure serializes all the AP processors through an Init sequence. It must be
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;noted that APs arrive here very raw...ie: real mode, no stack.
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;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC
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;IS IN MACHINE CODE.
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;-------------------------------------------------------------------------------------
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RendezvousFunnelProcStart:
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; At this point CS = 0x(vv00) and ip= 0x0.
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; Save BIST information to ebp firstly
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BITS 16
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mov ebp, eax ; Save BIST information
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mov ax, cs
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mov ds, ax
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mov es, ax
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mov ss, ax
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xor ax, ax
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mov fs, ax
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mov gs, ax
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2021-02-09 14:58:01 +01:00
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mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart)
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2016-07-20 16:44:39 +02:00
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mov ebx, [si]
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2021-02-09 14:58:01 +01:00
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mov si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment)
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2017-12-29 02:12:54 +01:00
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mov edx, [si]
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;
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; Get start address of 32-bit code in low memory (<1MB)
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;
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2021-02-09 14:58:01 +01:00
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mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeTransitionMemory)
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2016-07-20 16:44:39 +02:00
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2021-02-09 14:58:01 +01:00
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mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile)
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2016-07-20 16:44:39 +02:00
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o32 lgdt [cs:si]
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2017-12-29 02:12:54 +01:00
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;
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; Switch to protected mode
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;
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mov eax, cr0 ; Get control register 0
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or eax, 000000003h ; Set PE bit (bit #0) & MP
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mov cr0, eax
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; Switch to 32-bit code (>1MB)
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o32 jmp far [cs:di]
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;
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; Following code must be copied to memory with type of EfiBootServicesCode.
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; This is required if NX is enabled for EfiBootServicesCode of memory.
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;
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BITS 32
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Flat32Start: ; protected mode entry point
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mov ds, dx
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mov es, dx
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mov fs, dx
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mov gs, dx
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mov ss, dx
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2016-07-29 15:13:34 +02:00
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;
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; Enable execute disable bit
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;
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2021-02-09 14:58:01 +01:00
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mov esi, MP_CPU_EXCHANGE_INFO_FIELD (EnableExecuteDisable)
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2017-12-29 02:12:54 +01:00
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cmp byte [ebx + esi], 0
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jz SkipEnableExecuteDisableBit
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2016-07-29 15:13:34 +02:00
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mov ecx, 0c0000080h ; EFER MSR number
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rdmsr ; Read EFER
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bts eax, 11 ; Enable Execute Disable Bit
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wrmsr ; Write EFER
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SkipEnableExecuteDisableBit:
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2017-12-29 02:12:54 +01:00
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;
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; Enable PAE
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;
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2016-07-20 16:44:39 +02:00
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mov eax, cr4
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bts eax, 5
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2019-08-01 11:58:24 +02:00
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2021-02-09 14:58:01 +01:00
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mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Enable5LevelPaging)
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2019-08-01 11:58:24 +02:00
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cmp byte [ebx + esi], 0
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jz SkipEnable5LevelPaging
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;
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; Enable 5 Level Paging
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;
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bts eax, 12 ; Set LA57=1.
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SkipEnable5LevelPaging:
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2016-07-20 16:44:39 +02:00
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mov cr4, eax
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2017-12-29 02:12:54 +01:00
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;
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; Load page table
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;
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2021-02-09 14:58:01 +01:00
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mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3) ; Save CR3 in ecx
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2017-12-29 02:12:54 +01:00
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mov ecx, [ebx + esi]
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2016-07-20 16:44:39 +02:00
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mov cr3, ecx ; Load CR3
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2017-12-29 02:12:54 +01:00
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;
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; Enable long mode
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;
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2016-07-20 16:44:39 +02:00
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mov ecx, 0c0000080h ; EFER MSR number
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rdmsr ; Read EFER
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bts eax, 8 ; Set LME=1
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wrmsr ; Write EFER
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2017-12-29 02:12:54 +01:00
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;
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; Enable paging
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;
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2016-07-20 16:44:39 +02:00
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mov eax, cr0 ; Read CR0
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bts eax, 31 ; Set PG=1
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mov cr0, eax ; Write CR0
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2017-12-29 02:12:54 +01:00
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;
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; Far jump to 64-bit code
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;
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2021-02-09 14:58:01 +01:00
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mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeHighMemory)
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2017-12-29 02:12:54 +01:00
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add edi, ebx
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jmp far [edi]
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2016-07-20 16:44:39 +02:00
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BITS 64
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2021-12-09 04:27:30 +01:00
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2016-07-20 16:44:39 +02:00
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LongModeStart:
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2016-11-14 04:38:25 +01:00
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mov esi, ebx
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2022-08-25 04:55:04 +02:00
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; Set IDT table at the start of 64 bit code
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)]
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lidt [edi]
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2021-02-09 14:58:01 +01:00
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lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)]
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2016-11-14 04:38:25 +01:00
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cmp qword [edi], 1 ; ApInitConfig
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jnz GetApicId
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2017-10-23 09:02:36 +02:00
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; Increment the number of APs executing here as early as possible
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; This is decremented in C code when AP is finished executing
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mov edi, esi
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2021-02-09 14:58:01 +01:00
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add edi, MP_CPU_EXCHANGE_INFO_FIELD (NumApsExecuting)
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2017-10-23 09:02:36 +02:00
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lock inc dword [edi]
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2016-11-14 04:38:25 +01:00
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; AP init
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UefiCpuPkg/MpInitLib: Use XADD to avoid lock acquire/release
When AP firstly wakes up, MpFuncs.nasm contains below logic to assign
an unique ApIndex to each AP according to who comes first:
---ASM---
TestLock:
xchg [edi], eax
cmp eax, NotVacantFlag
jz TestLock
mov ecx, esi
add ecx, ApIndexLocation
inc dword [ecx]
mov ebx, [ecx]
Releaselock:
mov eax, VacantFlag
xchg [edi], eax
---ASM END---
"lock inc" cannot be used to increase ApIndex because not only the
global ApIndex should be increased, but also the result should be
stored to a local general purpose register EBX.
This patch learns from the NASM implementation of
InternalSyncIncrement() to use "XADD" instruction which can increase
the global ApIndex and store the original ApIndex to EBX in one
instruction.
With this patch, OVMF when running in a 255 threads QEMU spends about
one second to wakeup all APs. Original implementation needs more than
10 seconds.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2021-01-28 04:42:43 +01:00
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mov edi, esi
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2021-02-09 14:58:01 +01:00
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add edi, MP_CPU_EXCHANGE_INFO_FIELD (ApIndex)
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UefiCpuPkg/MpInitLib: Use XADD to avoid lock acquire/release
When AP firstly wakes up, MpFuncs.nasm contains below logic to assign
an unique ApIndex to each AP according to who comes first:
---ASM---
TestLock:
xchg [edi], eax
cmp eax, NotVacantFlag
jz TestLock
mov ecx, esi
add ecx, ApIndexLocation
inc dword [ecx]
mov ebx, [ecx]
Releaselock:
mov eax, VacantFlag
xchg [edi], eax
---ASM END---
"lock inc" cannot be used to increase ApIndex because not only the
global ApIndex should be increased, but also the result should be
stored to a local general purpose register EBX.
This patch learns from the NASM implementation of
InternalSyncIncrement() to use "XADD" instruction which can increase
the global ApIndex and store the original ApIndex to EBX in one
instruction.
With this patch, OVMF when running in a 255 threads QEMU spends about
one second to wakeup all APs. Original implementation needs more than
10 seconds.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2021-01-28 04:42:43 +01:00
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mov ebx, 1
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lock xadd dword [edi], ebx ; EBX = ApIndex++
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inc ebx ; EBX is CpuNumber
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2016-07-20 16:44:39 +02:00
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2016-11-14 04:38:25 +01:00
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; program stack
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2016-07-20 16:44:39 +02:00
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mov edi, esi
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2021-02-09 14:58:01 +01:00
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add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackSize)
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2016-11-14 04:38:25 +01:00
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mov eax, dword [edi]
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mov ecx, ebx
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inc ecx
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mul ecx ; EAX = StackSize * (CpuNumber + 1)
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2016-07-20 16:44:39 +02:00
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mov edi, esi
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2021-02-09 14:58:01 +01:00
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add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackStart)
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2016-07-20 16:44:39 +02:00
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add rax, qword [edi]
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mov rsp, rax
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UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
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;
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2021-12-09 04:27:30 +01:00
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; Setup the GHCB when AMD SEV-ES active.
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UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
|
|
|
;
|
2021-12-09 04:27:30 +01:00
|
|
|
OneTimeCall SevEsSetupGhcb
|
2016-11-14 04:38:25 +01:00
|
|
|
jmp CProcedureInvoke
|
|
|
|
|
|
|
|
|
|
GetApicId:
|
UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
|
|
|
;
|
2021-12-09 04:27:30 +01:00
|
|
|
; Use the GHCB protocol to get the ApicId when SEV-ES is active.
|
UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
|
|
|
;
|
2021-12-09 04:27:30 +01:00
|
|
|
OneTimeCall SevEsGetApicId
|
UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
|
|
|
|
|
|
|
|
DoCpuid:
|
2016-11-14 04:38:25 +01:00
|
|
|
mov eax, 0
|
|
|
|
|
cpuid
|
|
|
|
|
cmp eax, 0bh
|
UefiCpuPkg/MpInitLib: fix feature test for Extended Topology CPUID leaf
According to the Intel SDM (325462-060US / September 2016),
> INPUT EAX = 0BH: Returns Extended Topology Information
>
> [...] Software must detect the presence of CPUID leaf 0BH by verifying
> (a) the highest leaf index supported by CPUID is >= 0BH, and
> (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...]
The "GetApicId" sections in the Ia32 and X64 "MpFuncs.nasm" files do not
perform check (b).
This causes an actual bug in the following OVMF setup:
- Intel W3550 host processor <http://ark.intel.com/products/39720/>,
- the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU
visible to the guest should be exactly the same as the host CPU".
Under "GetApicId", check (a) passes: the CPUID level of the W3550 is
exactly 11 decimal. However, leaf 11 itself is not supported, therefore
EDX is set to zero:
> If a value entered for CPUID.EAX is less than or equal to the maximum
> input value and the leaf is not supported on that processor then 0 is
> returned in all the registers.
Because we don't check (b), the "GetProcessorNumber" section of the code
is reached with an initial APIC ID of 0 in EDX on all of the APs. Given
that "GetProcessorNumber" searches the
"MP_CPU_EXCHANGE_INFO.CpuInfo[*].InitialApicId" fields for a match, all
APs enter ApWakeupFunction() with an identical "NumApsExecuting"
parameter. This results in unpredictable guest behavior (crashes, reboots,
hangs etc).
Reorganize the "GetApicId" section and add the missing check in both
assembly files.
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-22 13:58:54 +01:00
|
|
|
jb NoX2Apic ; CPUID level below CPUID_EXTENDED_TOPOLOGY
|
|
|
|
|
|
|
|
|
|
mov eax, 0bh
|
|
|
|
|
xor ecx, ecx
|
|
|
|
|
cpuid
|
|
|
|
|
test ebx, 0ffffh
|
|
|
|
|
jz NoX2Apic ; CPUID.0BH:EBX[15:0] is zero
|
|
|
|
|
|
|
|
|
|
; Processor is x2APIC capable; 32-bit x2APIC ID is already in EDX
|
|
|
|
|
jmp GetProcessorNumber
|
|
|
|
|
|
|
|
|
|
NoX2Apic:
|
2016-11-14 04:38:25 +01:00
|
|
|
; Processor is not x2APIC capable, so get 8-bit APIC ID
|
|
|
|
|
mov eax, 1
|
|
|
|
|
cpuid
|
|
|
|
|
shr ebx, 24
|
|
|
|
|
mov edx, ebx
|
|
|
|
|
|
|
|
|
|
GetProcessorNumber:
|
|
|
|
|
;
|
|
|
|
|
; Get processor number for this AP
|
|
|
|
|
; Note that BSP may become an AP due to SwitchBsp()
|
|
|
|
|
;
|
|
|
|
|
xor ebx, ebx
|
2021-02-09 14:58:01 +01:00
|
|
|
lea eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)]
|
2021-01-07 00:53:23 +01:00
|
|
|
mov rdi, [eax]
|
2016-07-20 16:44:39 +02:00
|
|
|
|
2016-11-14 04:38:25 +01:00
|
|
|
GetNextProcNumber:
|
2021-02-09 14:58:01 +01:00
|
|
|
cmp dword [rdi + CPU_INFO_IN_HOB.InitialApicId], edx ; APIC ID match?
|
2016-11-14 04:38:25 +01:00
|
|
|
jz ProgramStack
|
2021-02-09 14:58:01 +01:00
|
|
|
add rdi, CPU_INFO_IN_HOB_size
|
2016-11-14 04:38:25 +01:00
|
|
|
inc ebx
|
2018-06-27 15:14:20 +02:00
|
|
|
jmp GetNextProcNumber
|
2016-11-14 04:38:25 +01:00
|
|
|
|
|
|
|
|
ProgramStack:
|
2021-02-09 14:58:01 +01:00
|
|
|
mov rsp, qword [rdi + CPU_INFO_IN_HOB.ApTopOfStack]
|
2016-07-20 16:44:39 +02:00
|
|
|
|
|
|
|
|
CProcedureInvoke:
|
2022-08-19 08:17:28 +02:00
|
|
|
;
|
|
|
|
|
; Reserve 8 bytes for CpuMpData.
|
|
|
|
|
; When the AP wakes up again via INIT-SIPI-SIPI, push 0 will cause the existing CpuMpData to be overwritten with 0.
|
|
|
|
|
; CpuMpData is filled in via InitializeApData() during the first time INIT-SIPI-SIPI,
|
|
|
|
|
; while overwirrten may occurs when under ApInHltLoop but InitFlag is not set to ApInitConfig.
|
|
|
|
|
; Therefore reservation is implemented by sub rsp instead of push 0.
|
|
|
|
|
;
|
|
|
|
|
sub rsp, 8
|
2016-07-29 15:08:01 +02:00
|
|
|
push rbp ; Push BIST data at top of AP stack
|
|
|
|
|
xor rbp, rbp ; Clear ebp for call stack trace
|
2016-07-20 16:44:39 +02:00
|
|
|
push rbp
|
|
|
|
|
mov rbp, rsp
|
|
|
|
|
|
2022-08-19 08:17:28 +02:00
|
|
|
push qword 0 ; Push 8 bytes for alignment
|
2021-02-09 14:58:01 +01:00
|
|
|
mov rax, qword [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitializeFloatingPointUnits)]
|
2016-07-20 16:44:39 +02:00
|
|
|
sub rsp, 20h
|
|
|
|
|
call rax ; Call assembly function to initialize FPU per UEFI spec
|
|
|
|
|
add rsp, 20h
|
|
|
|
|
|
2017-10-23 08:45:44 +02:00
|
|
|
mov edx, ebx ; edx is ApIndex
|
2023-06-28 10:47:23 +02:00
|
|
|
mov rcx, qword [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuMpData)]
|
2016-07-20 16:44:39 +02:00
|
|
|
|
|
|
|
|
mov edi, esi
|
2021-02-09 14:58:01 +01:00
|
|
|
add edi, MP_CPU_EXCHANGE_INFO_FIELD (CFunction)
|
2016-07-20 16:44:39 +02:00
|
|
|
mov rax, qword [edi]
|
|
|
|
|
|
|
|
|
|
sub rsp, 20h
|
2016-07-29 15:08:01 +02:00
|
|
|
call rax ; Invoke C function
|
2016-07-20 16:44:39 +02:00
|
|
|
add rsp, 20h
|
2016-07-29 15:08:01 +02:00
|
|
|
jmp $ ; Should never reach here
|
2016-07-20 16:44:39 +02:00
|
|
|
|
2022-05-07 15:19:08 +02:00
|
|
|
;
|
|
|
|
|
; Required for the AMD SEV helper functions
|
|
|
|
|
;
|
|
|
|
|
%include "AmdSev.nasm"
|
UefiCpuPkg: Allow AP booting under SEV-ES
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This
sequence is intercepted by the hypervisor, which sets the AP's registers
to the values requested by the sequence. At that point, the hypervisor can
start the AP, which will then begin execution at the appropriate location.
Under SEV-ES, AP booting presents some challenges since the hypervisor is
not allowed to alter the AP's register state. In this situation, we have
to distinguish between the AP's first boot and AP's subsequent boots.
First boot:
Once the AP's register state has been defined (which is before the guest
is first booted) it cannot be altered. Should the hypervisor attempt to
alter the register state, the change would be detected by the hardware
and the VMRUN instruction would fail. Given this, the first boot for the
AP is required to begin execution with this initial register state, which
is typically the reset vector. This prevents the BSP from directing the
AP startup location through the INIT-SIPI-SIPI sequence.
To work around this, the firmware will provide a build time reserved area
that can be used as the initial IP value. The hypervisor can extract this
location value by checking for the SEV-ES reset block GUID that must be
located 48-bytes from the end of the firmware. The format of the SEV-ES
reset block area is:
0x00 - 0x01 - SEV-ES Reset IP
0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16]
0x04 - 0x05 - Size of the SEV-ES reset block
0x06 - 0x15 - SEV-ES Reset Block GUID
(00f771de-1a7e-4fcb-890e-68c77e2fb44e)
The total size is 22 bytes. Any expansion to this block must be done
by adding new values before existing values.
The hypervisor will use the IP and CS values obtained from the SEV-ES
reset block to set as the AP's initial values. The CS Segment Base
represents the upper 16 bits of the CS segment base and must be left
shifted by 16 bits to form the complete CS segment base value.
Before booting the AP for the first time, the BSP must initialize the
SEV-ES reset area. This consists of programming a FAR JMP instruction
to the contents of a memory location that is also located in the SEV-ES
reset area. The BSP must program the IP and CS values for the FAR JMP
based on values drived from the INIT-SIPI-SIPI sequence.
Subsequent boots:
Again, the hypervisor cannot alter the AP register state, so a method is
required to take the AP out of halt state and redirect it to the desired
IP location. If it is determined that the AP is running in an SEV-ES
guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the
AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in
a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence
is recognized, the hypervisor will resume the AP. At this point the AP
must transition from the current 64-bit long mode down to 16-bit real
mode and begin executing at the derived location from the INIT-SIPI-SIPI
sequence.
Another change is around the area of obtaining the (x2)APIC ID during AP
startup. During AP startup, the AP can't take a #VC exception before the
AP has established a stack. However, the AP stack is set by using the
(x2)APIC ID, which is obtained through CPUID instructions. A CPUID
instruction will cause a #VC, so a different method must be used. The
GHCB protocol supports a method to obtain CPUID information from the
hypervisor through the GHCB MSR. This method does not require a stack,
so it is used to obtain the necessary CPUID information to determine the
(x2)APIC ID.
The new 16-bit protected mode GDT entry is used in order to transition
from 64-bit long mode down to 16-bit real mode.
A new assembler routine is created that takes the AP from 64-bit long mode
to 16-bit real mode. This is located under 1MB in memory and transitions
from 64-bit long mode to 32-bit compatibility mode to 16-bit protected
mode and finally 16-bit real mode.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2020-08-12 22:21:42 +02:00
|
|
|
|
2022-05-07 15:19:08 +02:00
|
|
|
RendezvousFunnelProcEnd:
|
2016-07-20 16:47:47 +02:00
|
|
|
|
2023-03-01 07:09:52 +01:00
|
|
|
;-------------------------------------------------------------------------------------
|
|
|
|
|
; AsmRelocateApLoop (MwaitSupport, ApTargetCState, TopOfApStack, CountTofinish, Cr3);
|
|
|
|
|
; This function is called during the finalizaiton of Mp initialization before booting
|
|
|
|
|
; to OS, and aim to put Aps either in Mwait or HLT.
|
|
|
|
|
;-------------------------------------------------------------------------------------
|
|
|
|
|
; +----------------+
|
|
|
|
|
; | Cr3 | rsp+40
|
|
|
|
|
; +----------------+
|
|
|
|
|
; | CountTofinish | r9
|
|
|
|
|
; +----------------+
|
|
|
|
|
; | TopOfApStack | r8
|
|
|
|
|
; +----------------+
|
|
|
|
|
; | ApTargetCState | rdx
|
|
|
|
|
; +----------------+
|
|
|
|
|
; | MwaitSupport | rcx
|
|
|
|
|
; +----------------+
|
|
|
|
|
; | the return |
|
|
|
|
|
; +----------------+ low address
|
|
|
|
|
|
|
|
|
|
AsmRelocateApLoopGenericStart:
|
|
|
|
|
mov rax, r9 ; CountTofinish
|
|
|
|
|
lock dec dword [rax] ; (*CountTofinish)--
|
|
|
|
|
|
|
|
|
|
mov rax, [rsp + 40] ; Cr3
|
|
|
|
|
; Do not push on old stack, since old stack is not mapped
|
|
|
|
|
; in the page table pointed by cr3
|
|
|
|
|
mov cr3, rax
|
|
|
|
|
mov rsp, r8 ; TopOfApStack
|
|
|
|
|
|
|
|
|
|
MwaitCheckGeneric:
|
|
|
|
|
cmp cl, 1 ; Check mwait-monitor support
|
|
|
|
|
jnz HltLoopGeneric
|
|
|
|
|
mov rbx, rdx ; Save C-State to ebx
|
|
|
|
|
|
|
|
|
|
MwaitLoopGeneric:
|
|
|
|
|
cli
|
|
|
|
|
mov rax, rsp ; Set Monitor Address
|
2023-03-21 08:29:59 +01:00
|
|
|
sub eax, 8 ; To ensure the monitor address is in the page table
|
2023-03-01 07:09:52 +01:00
|
|
|
xor ecx, ecx ; ecx = 0
|
|
|
|
|
xor edx, edx ; edx = 0
|
|
|
|
|
monitor
|
|
|
|
|
mov rax, rbx ; Mwait Cx, Target C-State per eax[7:4]
|
|
|
|
|
shl eax, 4
|
|
|
|
|
mwait
|
|
|
|
|
jmp MwaitLoopGeneric
|
|
|
|
|
|
|
|
|
|
HltLoopGeneric:
|
|
|
|
|
cli
|
|
|
|
|
hlt
|
|
|
|
|
jmp HltLoopGeneric
|
|
|
|
|
|
|
|
|
|
AsmRelocateApLoopGenericEnd:
|
|
|
|
|
|
2016-07-20 16:44:39 +02:00
|
|
|
;-------------------------------------------------------------------------------------
|
|
|
|
|
; AsmGetAddressMap (&AddressMap);
|
|
|
|
|
;-------------------------------------------------------------------------------------
|
|
|
|
|
global ASM_PFX(AsmGetAddressMap)
|
|
|
|
|
ASM_PFX(AsmGetAddressMap):
|
2022-05-07 14:34:36 +02:00
|
|
|
lea rax, [RendezvousFunnelProcStart]
|
2021-02-09 14:58:01 +01:00
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddress], rax
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], LongModeStart - RendezvousFunnelProcStart
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize], RendezvousFunnelProcEnd - RendezvousFunnelProcStart
|
2023-03-01 07:09:52 +01:00
|
|
|
lea rax, [AsmRelocateApLoopGenericStart]
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddressGeneric], rax
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSizeGeneric], AsmRelocateApLoopGenericEnd - AsmRelocateApLoopGenericStart
|
2023-03-01 07:09:53 +01:00
|
|
|
lea rax, [AsmRelocateApLoopAmdSevStart]
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddressAmdSev], rax
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSizeAmdSev], AsmRelocateApLoopAmdSevEnd - AsmRelocateApLoopAmdSevStart
|
2021-02-09 14:58:01 +01:00
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset], Flat32Start - RendezvousFunnelProcStart
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset], SwitchToRealProcStart - Flat32Start
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOffset], PM16Mode - RendezvousFunnelProcStart
|
|
|
|
|
mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSize], SwitchToRealProcEnd - PM16Mode
|
2016-07-20 16:44:39 +02:00
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
;-------------------------------------------------------------------------------------
|
|
|
|
|
;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is
|
2016-07-29 15:08:01 +02:00
|
|
|
;about to become an AP. It switches its stack with the current AP.
|
2016-07-20 16:44:39 +02:00
|
|
|
;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);
|
|
|
|
|
;-------------------------------------------------------------------------------------
|
|
|
|
|
global ASM_PFX(AsmExchangeRole)
|
|
|
|
|
ASM_PFX(AsmExchangeRole):
|
|
|
|
|
; DO NOT call other functions in this function, since 2 CPU may use 1 stack
|
|
|
|
|
; at the same time. If 1 CPU try to call a function, stack will be corrupted.
|
|
|
|
|
|
|
|
|
|
push rax
|
|
|
|
|
push rbx
|
|
|
|
|
push rcx
|
|
|
|
|
push rdx
|
|
|
|
|
push rsi
|
|
|
|
|
push rdi
|
|
|
|
|
push rbp
|
|
|
|
|
push r8
|
|
|
|
|
push r9
|
|
|
|
|
push r10
|
|
|
|
|
push r11
|
|
|
|
|
push r12
|
|
|
|
|
push r13
|
|
|
|
|
push r14
|
|
|
|
|
push r15
|
|
|
|
|
|
|
|
|
|
; rsi contains MyInfo pointer
|
|
|
|
|
mov rsi, rcx
|
|
|
|
|
|
|
|
|
|
; rdi contains OthersInfo pointer
|
|
|
|
|
mov rdi, rdx
|
|
|
|
|
|
|
|
|
|
pushfq
|
|
|
|
|
|
|
|
|
|
; Store the its StackPointer
|
2021-02-09 14:58:01 +01:00
|
|
|
mov [rsi + CPU_EXCHANGE_ROLE_INFO.StackPointer], rsp
|
2016-07-20 16:44:39 +02:00
|
|
|
|
|
|
|
|
; update its switch state to STORED
|
2021-02-09 14:58:01 +01:00
|
|
|
mov byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED
|
2016-07-20 16:44:39 +02:00
|
|
|
|
|
|
|
|
WaitForOtherStored:
|
|
|
|
|
; wait until the other CPU finish storing its state
|
2021-02-09 14:58:01 +01:00
|
|
|
cmp byte [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_STORED
|
2016-07-20 16:44:39 +02:00
|
|
|
jz OtherStored
|
|
|
|
|
pause
|
|
|
|
|
jmp WaitForOtherStored
|
|
|
|
|
|
|
|
|
|
OtherStored:
|
|
|
|
|
|
|
|
|
|
; load its future StackPointer
|
2021-02-09 14:58:01 +01:00
|
|
|
mov rsp, [rdi + CPU_EXCHANGE_ROLE_INFO.StackPointer]
|
2016-07-20 16:44:39 +02:00
|
|
|
|
|
|
|
|
; update the other CPU's switch state to LOADED
|
2021-02-09 14:58:01 +01:00
|
|
|
mov byte [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED
|
2016-07-20 16:44:39 +02:00
|
|
|
|
|
|
|
|
WaitForOtherLoaded:
|
|
|
|
|
; wait until the other CPU finish loading new state,
|
|
|
|
|
; otherwise the data in stack may corrupt
|
2021-02-09 14:58:01 +01:00
|
|
|
cmp byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE_LOADED
|
2016-07-20 16:44:39 +02:00
|
|
|
jz OtherLoaded
|
|
|
|
|
pause
|
|
|
|
|
jmp WaitForOtherLoaded
|
|
|
|
|
|
|
|
|
|
OtherLoaded:
|
|
|
|
|
; since the other CPU already get the data it want, leave this procedure
|
|
|
|
|
popfq
|
|
|
|
|
|
|
|
|
|
pop r15
|
|
|
|
|
pop r14
|
|
|
|
|
pop r13
|
|
|
|
|
pop r12
|
|
|
|
|
pop r11
|
|
|
|
|
pop r10
|
|
|
|
|
pop r9
|
|
|
|
|
pop r8
|
|
|
|
|
pop rbp
|
|
|
|
|
pop rdi
|
|
|
|
|
pop rsi
|
|
|
|
|
pop rdx
|
|
|
|
|
pop rcx
|
|
|
|
|
pop rbx
|
|
|
|
|
pop rax
|
|
|
|
|
|
|
|
|
|
ret
|
