The definitions are required by certain platform initialization
code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Reviewed-by: Amy Chan <amy.chan@intel.com>
Per UEFI spec the successful returning of boot option triggers boot
to UI. But when the BootNext just points to UI, it causes confusing.
So the patch avoids booting to UI again when the BootNext points to
UI.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
When we try to cd up two levels using the "../.." notation we
only go up one level. This patch fix this bug.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This patch adds the NORETURN attribute to the function that transfers
to the PEI phase, along with an UNREACHABLE() call at the end to
avoid false warnings.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This patch adds the NORETURN attribute to functions that transfer to
other phases, along with an UNREACHABLE() call at the end to avoid
false warnings.
DxeIpl has been excluded as its main function returns a status.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
When a variable is compared to NULL as part of an ASSERT() call, the
code implies that the variable may be NULL. Certain Static Analyzers,
such as the Clang Static Analyzer, then issue false warnings for any
untested access of that pointer, even though that defeats the
intention behind ASSERT(). This patch flags the position after
_ASSERT() as unreachable for Static Analyzers to indicate that if the
variable is NULL, execution cannot pass.
As the ANALYZER-prefixed version is used, the executables will not
have any code stripped during compilation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The NORETURN attribute informs compilers and analyzers that the flagged
function cannot return. This may improve the quality of the optimizations.
The UNREACHABLE() macro informs compilers and analyzers that its position
cannot be reached, for example eliminating implicit returns.
It is recommended to be used together with the NORETURN attribute to prevent
warnings regarding the function flagged as 'noreturn' returning.
The ANALYZER-prefixed versions have the same effects, but exclude compilers.
They may be used to surpress warnings of static analyzers, such as possible
dereferencing of a NULL pointer when dereferencing it after having checked it
via ASSERT().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
The patch fixed a bug in UefiHandleParsingLib to show handle's loaded
image device path.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
v2:
* Use goto to simplify code logic.
This patch is used to replace ASSERT with error handling in
DnsDxe driver.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
This patch is used to refine the code by removing ASSERT and
using error handling in IpSecDxe driver.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jaben Carsey <jaben.carsey@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Siyuan Fu <siyuan.fu@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
In current UI code, we use oneof opcode without storage for language
menu. If we change the language form A->B, then go to another form and
then go back to the front page, the language menu always shows A. Now
we fix this issue by retrieving the value of oneof opcode(language menu)
when display it.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The connect all action has been done in UiApp,
no need to do it when update boot manager form.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
If the connect all action has not been performed before.
We do it in UiApp now.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
When Hii variable is not present and if we try to update a variable offset
with some value, we are creating a new variable by Zeroing all the variable
offsets except the one which we are trying to update.
This will override all the other variable default values which are
programmed as a part of initial PCD definition.
DXE PCD driver could be enhanced to combine the DynamicHii
PCDs(related to same variable) default values and only update the offset
PcdSetXXX want to set, then set the combined values to variable.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
As per FSP 2.0 spec, FSP shall not trigger system reset and instead it
shall return from the FSP API to the BL/Wrapper with the required reset
type. The changes are to handle the ResetRequired return code from FSP
APIs and provide lib interface for platform to trigger the actual reset.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Amy Chan <amy.chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
The output of "dh <handle>" originally is like below:
12C: USBIO DevicePath(x0)/Pci(0x14,0x0)/USB(0x6,0x0))
The device path part is very confusing. Use ".." in front of the
partially displayed device path is better and it also aligns to
the example output in Shell spec.
12C: USBIO DevicePath(..)/Pci(0x14,0x0)/USB(0x6,0x0))
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
This patch is used to fix unspecified address use case in
ConstructSpdIndexer() function. Indexer->Name for
ConstructSpdIndexer is unspecified, that will be a problem
for UnicodeStrToAsciiStr.
This patch also refine the code by removing ASSERT and user
error handling.
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Zeng Star <star.zeng@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
defined values of EFI_MTFTP6_ERRORCODE_ILLEGAL_OPERATION and
EFI_MTFTP6_ERRORCODE_FILE_ALREADY_EXISTS are the same. This patch
corrects the value of EFI_MTFTP6_ERRORCODE_ILLEGAL_OPERATION to 4.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Sriram Subramanian <sriram-s@hpe.com>
Reviewed-By: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Besides Split FSP binary, we added some more feature to SplitFspBin tool.
Here we add user manual for it to describe all usage.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
Reviewed by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
For current implementation, if the device is pyrite type, driver
will suppress the "keep user data" option. Base on the feedback
from user, they prefer to keep the menu but gray out it. Now base
on this feedback to update the driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
OpRegion.
Add IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
Specification.
at https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf
Previous submission seems appears to be cut off. I do not know why.
Add missing part here.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
On some platforms, performing cache maintenance on regions that are backed
by NOR flash result in SErrors. Since cache maintenance is unnecessary in
that case, create a PEIM specific version that only performs said cache
maintenance in its constructor if the module is shadowed in RAM. To avoid
performing the cache maintenance if the MMU code is not used to begin with,
check that explicitly in the constructor.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This change corrects 3 problems in the PL011 driver.
1. The TRM states "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must
not be changed:...when the UART is enabled"
2. The TRM (3.3.8) describes logic requiring the UART to be disabled and
flushed before adjusting UARTCR.
3. Several redundant calls get made to PL011UartInitializePort, where
the characteristics do not change, but updating the registers can
cause glitches in the output stream.
The parameters are compared to the current state and no action taken if
no change of state is required.
Where an update is required, the specified logic is followed, and the
register updates only made when the UART is disabled.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
The interface to PL011UartInitializePort has changed in
ArmPlatformPkg/Drivers/PL011Uart with the title:
"ArmPlatformPkg: Add support to configure PL011 UART clock"
This patch updates the calls to PL011UartInitializePort(), in line with
that change, adding a parameter value using the PCD previously used
directly by the driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
On some platforms the UART clock is not the same for all the serial
ports. The PL011 driver must be capable of handling serial ports with
different clock rates, so must not rely on a PCD for the clock rate.
This patch allows the UART clock rate to be passed as a parameter
to PL011UartInitializePort(), which is called from the serial port
library. This patch also contains the corresponding changes in the
serial port library.
The PCD in Drivers/PL011Uart is replaced by an extra parameter for
PL011UartInitializePort. The PCD is moved to Library/PL011SerialPortLib
to supply the value to pass.
A corresponding patch to ArmVirtPkg is included in the same bundle to
align that with these changes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
The variable LineControl was initialised to zero, then updated in a
condition. This change converts that to a write in each branch of the
condition, removing the Write/Read/Modify/Write sequence.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
The PCDs used in the PL011 UART Driver and Serial Port Library are
inherently "fixed at build". This change updates the source to use
Fixed PCDs for these values. This improves clarity and efficiency.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
This cosmetic change only tidies things up in preparation for actual
updates. (This reflects responses to a previously submitted patch,
which has been split into several discrete changes.)
There are no functional changes in this commit.
Changes comprise:
Minor corrections to comment typos.
Minor formatting mods.
Expansion of function comments.
Remove OUT from UartBase parameter.
Addition of #define for "magic mumbers".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
When adding font package, there exists the case that only have the
EFI_HII_GIBT_GLYPH_DEFAULT or EFI_HII_GIBT_GLYPHS_DEFAULT glyph block
and use the default cell info in font package fixed header. In this
case, we can't get the correct baseline now. This patch is to fix this
issue by recalculating the baseline when the glyph block type is
EFI_HII_GIBT_GLYPH_DEFAULT or EFI_HII_GIBT_GLYPHS_DEFAULT.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Ruiyu Ni
Qiu Shumin
Marvin H?user
Star Zeng
Lu, ShifeiX A
Jiaxin Wu
Dandan Bi
Jiewen Yao
hegdenag
Zhang, Chao B
Satya Yarlagadda
Eric Dong
Ard Biesheuvel
Evan Lloyd