Commit Graph

64 Commits

Author SHA1 Message Date
Chasel, Chiu d75c07bc68 IntelFsp2Pkg/GenCfgOpt.py: remove tailing space from output file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212

UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.

Test: Verified the patch can remove tailing space in
      output header files when UPD DSC contains intentional
      tailing white space.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-09-28 11:58:49 +08:00
Chasel, Chiu 1d7eed4182 IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignment
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211

For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.

The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
  assign offset for all UPD automatically. In this case no
  need to manually hardcode offset to all UPD in DSC.

. If UPD offset in DSC file are all not '*', GenCfgOpt.py
  will use hardcoded offset directly (original usage model)

. Tool does not support mixing scenario so UPD offset in DSC
  should be all '*' or all hardcoded but not mixed.

In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.

Test: Verified by both UPD offset hardcoded or '*' in DSC and
      generated UPD header files are correct.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-09-28 11:58:49 +08:00
Chasel, Chiu ccacc4d273 IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210

FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.

Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-09-28 11:58:49 +08:00
shenglei dab8d71dc6 IntelFsp2Pkg/BaseFspSwitchStackLib: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28 10:54:52 +08:00
shenglei 06e88b8bfb IntelFsp2Pkg/BaseFspPlatformLib: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28 10:54:42 +08:00
shenglei 80d49b5714 IntelFsp2Pkg/BaseFspCommonLib: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28 10:54:33 +08:00
shenglei 1d94f67b24 IntelFsp2Pkg/FspSecCore: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28 10:54:22 +08:00
Chasel, Chiu ed5de31189 IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812b
Commit formats had issues so reverted 9 commits
from IntelFsp2Pkg and IntelFsp2WrapperPkg.
Will re-submit them with correct formats.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2018-09-28 10:50:43 +08:00
Chasel, Chiu 737f812b00 GenCfgOpt.py: remove tailing space from output file
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212

UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.

Test: Verified the patch can remove tailing space in
      output header files when UPD DSC contains intentional
      tailing white space.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-09-28 08:44:46 +08:00
Chasel, Chiu 29933058fc IntelFsp2Pkg/GenCfgOpt.py: Support UPD offset auto assignment
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211

For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.

The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
  assign offset for all UPD automatically. In this case no
  need to manually hardcode offset to all UPD in DSC.

. If UPD offset in DSC file are all not '*', GenCfgOpt.py
  will use hardcoded offset directly (original usage model)

. Tool does not support mixing scenario so UPD offset in DSC
  should be all '*' or all hardcoded but not mixed.

In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.

Test: Verified by both UPD offset hardcoded or '*' in DSC and
      generated UPD header files are correct.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-09-28 08:39:25 +08:00
Chasel, Chiu bb88882b75 IntelFsp2Pkg/GenCfgOpt.py: support FixedAtBuild PCD
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210

FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.

Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-28 07:58:48 +08:00
Chasel, Chiu fbb44beba0 [PATCH v3 04/16] IntelFsp2Pkg/BaseFspSwitchStackLib: Remove unused
PCDs

The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-27 15:42:56 +08:00
Chasel, Chiu 54611eacfe [PATCH v3 03/16] IntelFsp2Pkg/BaseFspPlatformLib: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-27 15:42:56 +08:00
Chasel, Chiu 47042f60e4 [PATCH v3 02/16] IntelFsp2Pkg/BaseFspCommonLib: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.

gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-27 15:42:56 +08:00
Chasel, Chiu e8208100c9 [PATCH v3 01/16] IntelFsp2Pkg/FspSecCore: Remove unused PCDs
The PCDs below are unused, so they have been removed from inf.

gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-27 15:42:56 +08:00
Chasel, Chiu 9062ab4787 IntelFsp2Pkg: Fix typo in SplitFspBin
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
2018-09-21 07:38:09 +08:00
Liming Gao e37bb20c7b IntelFsp2Pkg: Clean up source files
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-06-28 11:19:43 +08:00
Chasel, Chiu cc0d998b8b IntelFsp2Pkg: SplitFspBin.py to support x64 drivers
FSP binary potentially can include X64 drivers to
simplify implementation or support new features so
update SplitFspBin.py to support x64 image headers.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2018-06-25 08:11:30 +08:00
Chasel, Chiu 37431eb1fe IntelFsp2Pkg-Tools: GenCfgOpt.py shouldn't include specific UPD name
PcdSerialIoUartDebugEnable UPD is platform specific and should not
be included in generic GenCfgOpt.py script. Remove this and platform
DSC should control the default value instead.

Cc: Jiewen Yao <Jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
2017-11-08 20:44:29 +08:00
Liming Gao 034b941894 IntelFsp2Pkg: Update Section Name in INF files
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-10 18:10:23 +08:00
Song, BinX c69071bd7e IntelFsp2Pkg: Fix build error with WHOLEARCHIVE option
Add empty TempRamInitApi function to fix
build error with WHOLEARCHIVE option

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bell Song <binx.song@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-08-25 14:32:50 +08:00
Michael D Kinney 2a98de0344 edk2: Move License.txt file to root
https://bugzilla.tianocore.org/show_bug.cgi?id=642

Add top level License.txt file with the BSD 2-Clause
License that is used by the majority of the EKD II open
source project content.  Merge copyright statements
from the BSD 2-Clause License files in each package
directory and remove the duplication License.txt
file from package directories.

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-08-03 11:02:17 -07:00
Michael D Kinney bbdd3bad1b edk2: Move TianoCore Contribution Agreement to root
https://bugzilla.tianocore.org/show_bug.cgi?id=629

Move Contributions.txt that contains the TianoCore
Contribution Agreement 1.0 to the root of the edk2
repository and remove the duplicate Contributions.txt
files from all packages.

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-08-03 11:01:53 -07:00
Hao Wu 4aabee6980 IntelFsp2Pkg: Convert files to CRLF line ending
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-04-06 15:42:56 +08:00
Thomaiyar, Richard Marian ba8ea42738 IntelFsp2Pkg: Raise exception for invalid BSF option
Raise exception for invalid BSF option in GenCfgOpt.py

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-03-16 22:07:04 +08:00
Jiewen Yao e8911d052a IntelFsp2Pkg: Add Readme.md
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-03-13 08:54:29 +08:00
edk2-devel On Behalf Of rthomaiy e4408576df Make [-D Macros] as optional argument for GenCfgOpt
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-03-01 14:57:58 +08:00
Zeng, Star 60131098f3 IntelFsp2Pkg: 41d739e breaks flat tree build
There may be no environment variable PACKAGES_PATH defined
in flat tree, then 41d739e breaks flat tree build.
This patch is to update GenCfgOpt.py to be compatible with
both flat tree and package path build.

Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Tested-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
2016-12-05 14:17:23 +08:00
Thomaiyar, Richard Marian 41d739e4ec IntelFsp2Pkg: Add PACKAGES_PATH support
Add PACKAGES_PATH support in GenCfgOpt.py

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-30 14:37:45 +08:00
Thomaiyar, Richard Marian 0e3f9ee1d6 IntelFsp2Pkg: Use FspSiliconInitDone2 API
Use FspSiliconInitDone2 API in Notify Phase

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-24 16:27:22 +08:00
Thomaiyar, Richard Marian f56ae7bf82 IntelFsp2Pkg: Support to return error status from FSP API done
Added FspMemoryInitDone2, FspTempRamExitDone2, FspSiliconInitDone2
to return error status to Boot Loader for FSP API calls.
To maintain backward compatibility existing functions
(FspMemoryInitDone, FspTempRamExitDone, FspSiliconInitDone)
declaration left untouched.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-11-14 12:11:05 +08:00
Satya Yarlagadda c44f9a42d4 IntelFsp2Pkg: Removing FSP Data Table
FSP Base address is part of FSP_INFO_HEADER and we don't need additional
table to report the base address of FSP components. we expect Boot
loaders to parse the FSP INFO Header to get the base address. Also, this
the FSP_DATA_TABLE is not defined in the FSP EAS and we don't see a need
for it.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-10-28 23:25:15 +08:00
Yarlagadda, Satya P 19d29d358f IntelFsp2Pkg: Added changes to enable FPDT performance measurements
IntelFsp2Pkg:
1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the
Perf Data from FSP Global data.
2.Replaced the hard coded perf ids to use the standard defines
from FspStatuscode.h
3.Add the PerfData form Fsp Global data ( for TempRaminit entry,
TempramInit exit, memoryinit entry) to FPDT entries

IntelFsp2WrapperPkg:
  Moved the code to add the FSP FPDT records and wrapper FPDT records
from ReadytoBoot event to EndofFirmware event

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-10-27 14:19:44 +08:00
Gary Lin 058dcbf2b2 IntelFsp2Pkg: Fix typos in comments
- tempory -> temporary
- immediatly -> immediately
- permenent -> permanent
- funciton -> function

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-10-24 09:26:31 +08:00
Maurice Ma 08354c3448 IntelFsp2Pkg/FspSecCore: Make FSP functions position independent
The current AsmGetFspInfoHeader function in FspHeader.nasm is
position dependent code since it uses absolute address. Change
to use relative address instead to make it position independent.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-10-12 20:57:45 -07:00
Maurice Ma e8a70885d8 IntelFsp2Pkg/Tools: Add PE32 section rebasing support
The current SplitFspBin.py can only support TE image format
rebasing in an FSP binary. This patch adds PE32 image format
rebasing support.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Satya Yarlagadda <Satya.p.yarlagadda@intel.com>
2016-10-05 20:07:58 -07:00
Satya Yarlagadda cd3692b11e IntelFsp2Pkg: Align #Pragma in UPD header files to rest of EDK2 Pkgs
Changed the GenCfgOpt.py script to insert pragma pack(1) instead of
pragma pack (push, 1) in the upd header files generated during fsp build.
This is to align with rest of the EDKII pkgs pragma pack usage.

Also, this scripts generates UnusedUpdSpace for UPD address gaps.
Currently it uses UIN16/UINT32/UINT64 for 2/4/8 bytes instead of UINT8[],
thus causing upd space waste to have Natural Alignment. Hence changed the
script to use UINT8[] for any unusedUpd fields above 1 byte.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-20 11:38:11 +08:00
Giri P Mudusuru 86079a4d21 IntelFsp2Pkg: Fix typo and comments
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-08-31 14:27:54 +08:00
Yarlagadda, Satya P 90fadfc00a IntelFsp2Pkg: Add function to get FspInfoHeader before stack is ready
we need to locate the FSP Info Header before the stack is initialized to
access the cfg region for any UPD. Hence adding the
AsmGetFspInfoHeaderNoStack function to support it.

Note: This function is there in IntelFspPkg but got removed in IntelFsp2Pkg

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-23 08:09:33 +08:00
Mudusuru, Giri P 87c400e14c IntelFsp2Pkg: Converted PatchFvUserManual from .docx to .md format
Converted the the word format of the documentation into markdown format
for PatchFv.py

V2: updated the commit message descripton

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-08-08 20:57:05 +08:00
Mudusuru, Giri P eeb71f2900 IntelFsp2Pkg: Converted GenCfgOptUserManual from .docx to .md format
Converted the the word format of the documentation into markdown format
for GenCfgOpt.py

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-08-08 20:57:04 +08:00
Hao Wu bc8a17305d IntelFsp2Pkg DSC: Add build option to disable deprecated APIs
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated:

[BuildOptions]
  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-08-08 11:00:05 +08:00
Maurice Ma 7e9cf61205 IntelFsp2Pkg: Only include required header files in FspEas.h
Current FspEas.h file includes Uefi.h which also refers to lots of other
UEFI header files not used by FSP consumer. It caused many unnecessary
header file overhead for a bootloader that consumes FSP, such as coreboot.
This change reduces the required header file number down to 3.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-05 08:42:09 -07:00
Yarlagadda, Satya P 8265373e60 IntelFsp2Pkg: Locate FSP Info Header dynamically
we need to locate the FSP Info Header by calculating offset dynamically to
handle the scenario of FSP component is being rebased to different location.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-02 21:12:54 +08:00
Yarlagadda, Satya P 4c53eb72d5 IntelFsp2Pkg: Skip loading Microcode if MicrocodeCodeSize is zero
During asm to Nasm conversion, we missed the code to skip loading the
microcode and return success if the size is zero. Added additional check to
report error if the microcode size is not zero but less than 2 kB.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-07-27 09:08:43 +08:00
Jiewen Yao 31bd97f329 IntelFsp2Pkg: Add missing License.txt.
Add missing License.txt.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-26 10:52:03 +08:00
Satya Yarlagadda 40bc750914 IntelFsp2Pkg: Remove CarBase and CarSize from FSP_GLOBAL_DATA
CarBase and CarSize in Fsp Global data structure are no longer needed as
Boot loader doesn't pass them to FSP even in case that BL chooses to skip calling
the FspTempRamInit API. In case of FspTempramInit is called, we can use the PCDs
to identify the CarBase and Size. Hence we remove the relevant code.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-07-23 09:20:04 +08:00
Liming Gao 970a9a8ba3 IntelFsp2Pkg: Add missing modules in Package DSC
Package DSC is used to verify the module source build.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-20 13:11:32 +08:00
Satya Yarlagadda 35126af96c IntelFsp2Pkg BaseFspPlatformLib: Remove Boot Loader tempram Migration
In FSP2.0, Boot loader should migrate its temp ram before
calling the tempramexit API to tear down the tempram. so, we don't need the
function to migrate the BL TempRam in the IntelFsp2Pkg.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-07-18 13:17:23 +08:00
Liming Gao f0fe58bc72 IntelFsp2Pkg SecFspSecPlatformLibNull: Remove MASM/GAS files
Keep NASM file only for new added modules.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-11 13:53:57 +08:00