The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware
that has some memory mapped locations that can trigger traditional SPI
interrupts. This allows some basic PCIe MSI capabilities.
Setup the SPI range that is mapped by the MSI window. This range is
described in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is
described as "GICv2m PCI Express MSI". In the future when these tables
are generated programmatically the information may be found in the
MSI_TYPER register as well.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18723 6f19259b-4bc3-4df7-8a09-765794883524
On Juno R1, the MAC address assigned to the PCI Gigabyte Ethernet device
as to be passed to the Linux Kernel.
The MAC address is passed to the Linux Kernel by means of the boot argument
"sky2.mac_address".
This patch adds this boot argument to the lists of boot arguments of the
two Juno R1 default boot options.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17095 6f19259b-4bc3-4df7-8a09-765794883524
Jeremy Linton
Olivier Martin
Ronald Cron