REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265
FSP should not override IDT table when it is initialized
by boot loader. IDT should be re-initialized in FSP only
when it is invalid.
To mitigate temporary memory usage a PCD
PcdFspMaxInterruptSupported created for platform to decide
how many interrupts the FSP IDT table can support.
Test: Verified on internal platform and boots successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1241
Add support for both API (original mode) and DISPATCH mode:
1. Add FspMode field from reserved byte of Global
Data Structure to tell which mode is selected by boot
loader. If boot loader invoking FSP-M API this field
will remain as default 0 (API mode), otherwise platform
FSP should set this field to 1 (Dispatch mode) when
initializing Global Data Structure.
2. gFspInApiModePpiGuid will be instaled when FSP running in API
mode and modules only for API mode should have this in depex.
3. If it is DISPATCH mode, FSP will return to PEI dispatcher,
not directly return to boot loader.
4. DISPATCH mode supports DXE NotifyPhase drivers so FSP
will not wait for PEI NotifyPhase callbacks, instead it
will install gFspReadyForNotifyPhasePpiGuid PPI for
platform to complete late initialization before transferring
to DXE.
Test: Verified FSP API and DISPATCH modes on 2 internal
platforms and both boot successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1231
Build system already support override PCD value by command
line so add this support to GenCfgOpt.py
Also update revision to 0.53
Test: Verified UPD header files generated can reflect different
PCD values from --pcd build command input
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Zhu Yonghong <yonghong.zhu@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212
UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.
Test: Verified the patch can remove tailing space in
output header files when UPD DSC contains intentional
tailing white space.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211
For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.
The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
assign offset for all UPD automatically. In this case no
need to manually hardcode offset to all UPD in DSC.
. If UPD offset in DSC file are all not '*', GenCfgOpt.py
will use hardcoded offset directly (original usage model)
. Tool does not support mixing scenario so UPD offset in DSC
should be all '*' or all hardcoded but not mixed.
In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.
Test: Verified by both UPD offset hardcoded or '*' in DSC and
generated UPD header files are correct.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210
FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.
Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Commit formats had issues so reverted 9 commits
from IntelFsp2Pkg and IntelFsp2WrapperPkg.
Will re-submit them with correct formats.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1212
UPD header files generated by GenCfgOpt.py may have
tailing white space from some of the UPD description in DSC,
especially when python script automatically switching lines
for long description string. This patch will always remove
tailing white space for UPD header files.
Test: Verified the patch can remove tailing space in
output header files when UPD DSC contains intentional
tailing white space.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1211
For reducing maintenance effort, the UPD offset can be
automatic assigned by GenCfgOpt.py following by alignment
requirements.
The usage model as below:
. If UPD offset in DSC file are all '*', GenCfgOpt.py will
assign offset for all UPD automatically. In this case no
need to manually hardcode offset to all UPD in DSC.
. If UPD offset in DSC file are all not '*', GenCfgOpt.py
will use hardcoded offset directly (original usage model)
. Tool does not support mixing scenario so UPD offset in DSC
should be all '*' or all hardcoded but not mixed.
In auto mode UPD offset will be assigned following natural
alignment (size aligned) rule and the whole structure size
will align to either 32bits or 64bits depends on maximal UPD
size in the structure.
Test: Verified by both UPD offset hardcoded or '*' in DSC and
generated UPD header files are correct.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1210
FixedAtBuild PCD is suggested to be used instead
of FeatureFlag PCD so extend this tool to support.
Also skipped PCDs which commented out by '#'.
Test: Verified with FixedAtBuild PCD for including or
excluding lines in generated UPD header files successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Gao Liming <liming.gao@intel.com>
Cc: Zhu Yonghong <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
PCDs
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
The PCDs below are unused, so they have been removed from inf.
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry
gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: shenglei <shenglei.zhang@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
FSP binary potentially can include X64 drivers to
simplify implementation or support new features so
update SplitFspBin.py to support x64 image headers.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
PcdSerialIoUartDebugEnable UPD is platform specific and should not
be included in generic GenCfgOpt.py script. Remove this and platform
DSC should control the default value instead.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Add empty TempRamInitApi function to fix
build error with WHOLEARCHIVE option
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bell Song <binx.song@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=642
Add top level License.txt file with the BSD 2-Clause
License that is used by the majority of the EKD II open
source project content. Merge copyright statements
from the BSD 2-Clause License files in each package
directory and remove the duplication License.txt
file from package directories.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
https://bugzilla.tianocore.org/show_bug.cgi?id=629
Move Contributions.txt that contains the TianoCore
Contribution Agreement 1.0 to the root of the edk2
repository and remove the duplicate Contributions.txt
files from all packages.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Andrew Fish <afish@apple.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Raise exception for invalid BSF option in GenCfgOpt.py
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
There may be no environment variable PACKAGES_PATH defined
in flat tree, then 41d739e breaks flat tree build.
This patch is to update GenCfgOpt.py to be compatible with
both flat tree and package path build.
Cc: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Tested-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Add PACKAGES_PATH support in GenCfgOpt.py
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Use FspSiliconInitDone2 API in Notify Phase
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Added FspMemoryInitDone2, FspTempRamExitDone2, FspSiliconInitDone2
to return error status to Boot Loader for FSP API calls.
To maintain backward compatibility existing functions
(FspMemoryInitDone, FspTempRamExitDone, FspSiliconInitDone)
declaration left untouched.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Richard Thomaiyar <richard.marian.thomaiyar@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
FSP Base address is part of FSP_INFO_HEADER and we don't need additional
table to report the base address of FSP components. we expect Boot
loaders to parse the FSP INFO Header to get the base address. Also, this
the FSP_DATA_TABLE is not defined in the FSP EAS and we don't see a need
for it.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
IntelFsp2Pkg:
1.Defined performance measure mask to mask the Perf id (Bits 63:56) of the
Perf Data from FSP Global data.
2.Replaced the hard coded perf ids to use the standard defines
from FspStatuscode.h
3.Add the PerfData form Fsp Global data ( for TempRaminit entry,
TempramInit exit, memoryinit entry) to FPDT entries
IntelFsp2WrapperPkg:
Moved the code to add the FSP FPDT records and wrapper FPDT records
from ReadytoBoot event to EndofFirmware event
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
The current AsmGetFspInfoHeader function in FspHeader.nasm is
position dependent code since it uses absolute address. Change
to use relative address instead to make it position independent.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
The current SplitFspBin.py can only support TE image format
rebasing in an FSP binary. This patch adds PE32 image format
rebasing support.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Satya Yarlagadda <Satya.p.yarlagadda@intel.com>
Changed the GenCfgOpt.py script to insert pragma pack(1) instead of
pragma pack (push, 1) in the upd header files generated during fsp build.
This is to align with rest of the EDKII pkgs pragma pack usage.
Also, this scripts generates UnusedUpdSpace for UPD address gaps.
Currently it uses UIN16/UINT32/UINT64 for 2/4/8 bytes instead of UINT8[],
thus causing upd space waste to have Natural Alignment. Hence changed the
script to use UINT8[] for any unusedUpd fields above 1 byte.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
we need to locate the FSP Info Header before the stack is initialized to
access the cfg region for any UPD. Hence adding the
AsmGetFspInfoHeaderNoStack function to support it.
Note: This function is there in IntelFspPkg but got removed in IntelFsp2Pkg
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Converted the the word format of the documentation into markdown format
for PatchFv.py
V2: updated the commit message descripton
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Converted the the word format of the documentation into markdown format
for GenCfgOpt.py
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated:
[BuildOptions]
*_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Current FspEas.h file includes Uefi.h which also refers to lots of other
UEFI header files not used by FSP consumer. It caused many unnecessary
header file overhead for a bootloader that consumes FSP, such as coreboot.
This change reduces the required header file number down to 3.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
we need to locate the FSP Info Header by calculating offset dynamically to
handle the scenario of FSP component is being rebased to different location.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
During asm to Nasm conversion, we missed the code to skip loading the
microcode and return success if the size is zero. Added additional check to
report error if the microcode size is not zero but less than 2 kB.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
CarBase and CarSize in Fsp Global data structure are no longer needed as
Boot loader doesn't pass them to FSP even in case that BL chooses to skip calling
the FspTempRamInit API. In case of FspTempramInit is called, we can use the PCDs
to identify the CarBase and Size. Hence we remove the relevant code.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
In FSP2.0, Boot loader should migrate its temp ram before
calling the tempramexit API to tear down the tempram. so, we don't need the
function to migrate the BL TempRam in the IntelFsp2Pkg.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/SecCarInit.asm to Ia32/SecCarInit.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/Stack.asm to Ia32/Stack.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/FspDebug.asm to Ia32/FspDebug.nasm
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Added new funtion in FSPCommonLib to update the FSP API return status with
the requested return status and return the control to the boot loader.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Besides Split FSP binary, we added some more feature to SplitFspBin tool.
Here we add user manual for it to describe all usage.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Enhanced the SplitFspBin tool in IntelFsp2Pkg to support:
- Rebase FSP 2.0 components to a different base address
- Display FSP 2.0 information header
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Adding defines from FSP EAS v2.0 section 11.2.2 Oem Status code.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
The current GenCfgOpt tool does not generate bit fields in BSF.
This change will allow bit fields to be created in BSF for a specific
FSP UPD item. The argument for the tool is also updated to be in sync
with the old usage model in IntelFspPkg.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Add doxygen style comment for structure definition.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Satya P Yarlagadda <satya.p.yarlagadda@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Add FSP2.0 support.
This series of patch is to support FSP2.0 specification at
https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf
Some major updates include:
1) One FSP binary is separated to multiple components:
FSP-T, FSP-M, FSP-S, and optional FSP-O.
Each component has its own configuration data region.
2) All FSP-APIs use same UPD format - FSP_UPD_HEADER.
3) Add EnumInitPhaseEndOfFirmware notifyphase.
4) FSP1.1/FSP1.0 compatibility is NOT maintained.
5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg,
to indicate that it is for FspWrapper only.
IntelFspPkg and IntelFspWrapperPkg will be deprecated.
The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg
and IntelFsp2WrapperPkg.
The old platform can still use IntelFspPkg and IntelFspWrapperPkg
for compatibility consideration.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
Chasel, Chiu
shenglei
Liming Gao
Song, BinX
Michael D Kinney
Hao Wu
Thomaiyar, Richard Marian
Jiewen Yao
edk2-devel On Behalf Of rthomaiy
Zeng, Star
Satya Yarlagadda
Gary Lin
Maurice Ma
Giri P Mudusuru