The binaries of ShellBinPkg are generated with ShellPkg project 16948.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16950 6f19259b-4bc3-4df7-8a09-765794883524
Based on MdePkg and BaseTools (r16948), FatPkg (r93)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16949 6f19259b-4bc3-4df7-8a09-765794883524
Juno R1 can run in two configurations:
- A57x2
- A57x2-A53x4
The Device Tree tell Linux which configuration has been selected.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16942 6f19259b-4bc3-4df7-8a09-765794883524
Remove the option to update the "Fdt" UEFI variable in the ARM BDS as
the "setfdt" EFI Shell command provides this service from now.
Remove the use of this variable in the legacy kernel boot loader and
use the FDT installed in the configuration table instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16940 6f19259b-4bc3-4df7-8a09-765794883524
The MIDR register of the CPU on which the UEFI firmware is running on
is used to infer if the platform is a Juno r0 or a Juno r1. The right
device path to the platform FDT is then stored in the
"gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" dynamic PCD.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16939 6f19259b-4bc3-4df7-8a09-765794883524
Remove the installation of the FDT for Juno into the UEFI Configuration
Table from the Juno specific DXE driver. Use the FdtPlatformDxe driver to
do it instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16938 6f19259b-4bc3-4df7-8a09-765794883524
Make the Unix Vlv2TbltDevicePkg scripts executable, add shebangs and skip the requirement to press a key when displaying usage text from Build_IFWI.sh.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bruce Cran <bruce.cran@gmail.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16936 6f19259b-4bc3-4df7-8a09-765794883524
The 'setfdt' EFI Shell command allows to define a new FDT
as the prefered one for development purposes. It allows to
trigger the run of the FDT installation process as well.
Please refer to the README.txt file for more comprehensive
description.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16934 6f19259b-4bc3-4df7-8a09-765794883524
The FdtPlatformDxe driver installs the FDT of the platform it
is running on into the UEFI Configuration table at the end of
the DXE phase.
Please refer to the README.txt file for a global overview of
the driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <Ronald.Cron@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16933 6f19259b-4bc3-4df7-8a09-765794883524
There are three FVP variants for the Base and Foundation models:
- model with GICv2 legacy memory map (same location as the Versatile Express model)
- model with GICv2 and Base model memory map
- model with GICv3 and Base model memory map
The new code detects the variants to load the appropriate device tree.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16932 6f19259b-4bc3-4df7-8a09-765794883524
Add a function to ArmVExpressDxe to identify the current platform we
are running on. This includes ARM32 and AArch64 models and hardware.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16931 6f19259b-4bc3-4df7-8a09-765794883524
Some boot entries might not have a EFI Device Path FilePath
attached to it (eg: EFI device Path for removable device path).
This patch allows a support loader to edit the EFI Device Path
and for instance add \EFI\BOOT\BOOT(ARM|AA64).EFI
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16930 6f19259b-4bc3-4df7-8a09-765794883524
- 'earlycon' is the new name for 'earlyprintk'
- Support Linux EFI stub by default
- The command line is expected to be in unicode when
booting an EFI application.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16928 6f19259b-4bc3-4df7-8a09-765794883524
ARM toolchain raises the build error:
Error #188-D: enumerated type mixed with another type
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16927 6f19259b-4bc3-4df7-8a09-765794883524
- GIC distributor needs to be programmed to target interrupts
on the boot CPU using the Interrupt Processor Targets Registers
- Enabling the GIC Distributor is different following the value
of GICD_CTLR.ARE_NS.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16926 6f19259b-4bc3-4df7-8a09-765794883524
Detect the video displays dynamically, and add them to the console and
error output variables.
Add a short-form, "wild card" USB_CLASS_DEVICE_PATH to the console input
variable, which causes the USB keyboard to be handled automatically.
Add the fixed location serial console to all of the console input, console
output, and error output variables.
This patch enables QEMU users to drop "addr=..." PCI address
specifications from the -device options (or to use whatever addresses they
like). For example, the following works:
-device VGA \
\
-device ich9-usb-ehci1,multifunction=on,id=ehci \
-device ich9-usb-uhci1,multifunction=on,masterbus=ehci.0,firstport=0 \
-device ich9-usb-uhci2,multifunction=on,masterbus=ehci.0,firstport=2 \
-device ich9-usb-uhci3,multifunction=on,masterbus=ehci.0,firstport=4 \
-device usb-kbd,bus=ehci.0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16924 6f19259b-4bc3-4df7-8a09-765794883524
In this patch we remove all dependencies on ARM BDS libraries. We also
remove empty and/or unneeded functions, includes, etc.
PlatformIntelBdsLib "goes back to basics" temporarily -- there are no
consoles configured, and it's practically not possible to interact with
the user interface. Bisection remains available in the sense that
"ArmVirtualizationQemu.dsc" continues to build and should boot preexistent
boot options, but user interaction does regress temporarily.
The reason for this is that it's preferable to keep this patch and the
next one separate for readability's sake -- they amount to a rewrite from
scratch.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16923 6f19259b-4bc3-4df7-8a09-765794883524
Some compilers requires an empty line at the end of the file.
ARM compiler version 5 is one of these compilers:
error #1-D: last line of file ends without a newline
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16918 6f19259b-4bc3-4df7-8a09-765794883524
SlotTypeAgp8X should be used per SMBIOS spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16917 6f19259b-4bc3-4df7-8a09-765794883524
Similarly to the previous patch, we can now multiplex input from the USB
keyboard.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16914 6f19259b-4bc3-4df7-8a09-765794883524
Alex Graf's QEMU patchset enables "-device VGA" for the virt machtype as
well. We can now include OvmfPkg/QemuVideoDxe in the firmware, and set
PcdDefaultConOutPaths such that the console output is multiplexed to the
video window as well. (Our platform BDS lib doesn't (yet) locate the VGA
device automatically.)
OvmfPkg/PlatformDxe is included too; it allows users to select a video
resolution. (Note that PcdSetupVideoHorizontalResolution and
PcdSetupVideoVerticalResolution are independent; see git commit 848834cb
(SVN r16311) for explanation.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16913 6f19259b-4bc3-4df7-8a09-765794883524
In the following call chain:
PlatformBdsPolicyBehavior()
PlatformBdsConnectConsole()
InitializeConsolePipe() x 3
BdsConnectDevicePath() [ArmPkg/Library/BdsLib/BdsFilePath.c]
the three InitializeConsolePipe() function calls pass through
- (&gST->ConsoleOutHandle, &gST->ConOut),
- (&gST->ConsoleInHandle, &gST->ConIn),
- (&gST->StandardErrorHandle, &gST->StdErr)
to BdsConnectDevicePath(), in ArmPkg's BdsLib.
At least when more than one console device paths are specified in the
ConIn / ConOut / ErrOut variables, the above resuls in:
- unchanged protocol interfaces (ConOut, ConIn, StdErr) in the system
table (because ConSplitterDxe installs its non-NULL interfaces first),
- but, changed handles in the system table.
This effectively separates the handle fields in the system table from the
protocol interfaces in the same that should always be associated with the
handles. The end result is that clients using the handles break (splitting
/ multiplexing doesn't work for them), while clients directly using the
protocol interfaces work.
Therefore, do not attempt to connect consoles separately. ConSplitterDxe
is dispatched before PlatformBdsPolicyBehavior() is called (the latter
happens in the BDS phase), and ConSplitterDxe installs virtual handles and
protocol interfaces for input / output / error.
BdsLibConnectAll() covers all devices, including consoles; as those
consoles are connected, ConPlatformDxe and ConSplitterDxe pick them up
nicely as "slaves". We just need to make sure that the variables are set
first, for the variables -> ConPlatformDxe -> ConSplitterDxe dependency
chain.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16912 6f19259b-4bc3-4df7-8a09-765794883524
If there is a PCI host, then PCI enumeration (which happens inside
BdsLibConnectAll()) blocks ACPI table installation (correctly). Make sure
we install ACPI tables before trying to direct-boot a QEMU kernel.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16911 6f19259b-4bc3-4df7-8a09-765794883524
Beyond including the foundational drivers in the DSC and FDF files, we
enable virtio-over-PCI, and turn on QemuBootOrderLib's OFW-to-UEFI device
path translation for PCI devices.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16910 6f19259b-4bc3-4df7-8a09-765794883524
The BarExisted() function in
"MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c" raises the TPL to
TPL_HIGH_LEVEL before accessing PCI config space.
The PciExpressLib instance under "MdePkg/Library/BasePciExpressLib" --
serving the PCI config space access -- calls
PcdGet64(PcdPciExpressBaseAddress) in turn, for each such call.
The PcdGet64() function, when issued at TPL_HIGH_LEVEL, triggers an
ASSERT(). PcdGet64() is based on a protocol in this UEFI phase, and
protocol handler services are not allowed above TPL_NOTIFY (see Table 23
"TPL Restrictions" in the UEFI spec).
Clone the library, and in a new constructor, cache the PCD in a global
variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16909 6f19259b-4bc3-4df7-8a09-765794883524
When there are no devices connected to the root bridge, no resources are
needed. GetProposedResources() currently considers this an invalid
condition (the PI spec doesn't regulate it).
Emitting an empty set of EFI_ACPI_ADDRESS_SPACE_DESCRIPTORs, followed by
the required EFI_ACPI_END_TAG_DESCRIPTOR, allows
PciHostBridgeResourceAllocator() [MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c]
to advance.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16908 6f19259b-4bc3-4df7-8a09-765794883524
According to Volume 5 of the PI spec, 10.8.2 PCI Host Bridge Resource
Allocation Protocol, SubmitResources(),
It is considered an error if no resource requests are submitted for a
PCI root bridge. If a PCI root bridge does not require any resources, a
zero-length resource request must explicitly be submitted.
Under MdeModulePkg/Bus/Pci/PciBusDxe/, we have:
PciHostBridgeResourceAllocator() [PciLib.c]
ConstructAcpiResourceRequestor(..., &AcpiConfig) [PciEnumerator.c]
PciResAlloc->SubmitResources(..., &AcpiConfig)
ASSERT_EFI_ERROR ()
If ConstructAcpiResourceRequestor() finds no resources to request (for
example because no PCI devices are on the root bridge), it places a
zero-length EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR followed by an
EFI_ACPI_END_TAG_DESCRIPTOR in "AcpiConfig"; satisfying the PI spec.
However, PciHostBridgeDxe's SubmitResources() function does not expect
such input; the following part of the code rejects it:
switch (Ptr->ResType) {
case 0:
//
// Check invalid Address Sapce Granularity
//
if (Ptr->AddrSpaceGranularity != 32) {
return EFI_INVALID_PARAMETER;
}
Skip EFI_ACPI_ADDRESS_SPACE_DESCRIPTORs with zero AddrLen early. Also,
allow PciHostBridgeResourceAllocator() to proceed to the AllocateResources
phase by setting "ResourceSubmited" to TRUE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16907 6f19259b-4bc3-4df7-8a09-765794883524
This is our MMIO space map:
> GCD:AddMemorySpace(Base=0000000010000000,Length=000000002EFF0000)
> GcdMemoryType = MMIO
> Capabilities = 0000000000000001
> Status = Success
> GCDMemType Range Capabilities Attributes
> ========== ================================= ================ ================
> NonExist 0000000000000000-0000000003FFFFFF 0000000000000000 0000000000000000
> MMIO 0000000004000000-0000000007FFFFFF C000000000000001 8000000000000001
NorFlashDxe adds this, but does not allocate it.
> NonExist 0000000008000000-000000000900FFFF 0000000000000000 0000000000000000
> MMIO 0000000009010000-0000000009010FFF C000000000000001 8000000000000001
Added by RealTimeClockRuntimeDxe, but also not allocated.
> NonExist 0000000009011000-000000000FFFFFFF 0000000000000000 0000000000000000
> MMIO 0000000010000000-000000003EFEFFFF C000000000000001 0000000000000000
Added by ourselves.
> NonExist 000000003EFF0000-000000003FFFFFFF 0000000000000000 0000000000000000
> SystemMem 0000000040000000-00000000BFFFFFFF 800000000000000F 0000000000000008*
> NonExist 00000000C0000000-0000FFFFFFFFFFFF 0000000000000000 0000000000000000
In the EfiPciHostBridgeAllocateResources phase, we allocate memory BARs
bottom up, from whichever MMIO range comes first and has room left.
Unfortunately, this places memory BARs into MMIO ranges that belong to
other devices. (Arguably, their respective drivers should not just add,
but immediately allocate those ranges as well.)
(
This problem is not seen in OVMF / PcAtChipsetPkg, because there we
allocate bottom-up from the range
[max(2GB, top-of-low-RAM), 0xFC000000).
(See the MMIO resource descriptor HOB created in MemMapInitialization()
[OvmfPkg/PlatformPei/Platform.c].)
That MMIO range fits in the static [2GB, 4GB) aperture given in
"mResAperture" in PcAtChipsetPkg/PciHostBridgeDxe; plus other MMIO
ranges (IO-APIC, HPET, LAPIC, flash chip) are higher than 0xFC000000.
Hence the bottom-up BAR allocation in OvmfPkg always finds the right
MMIO range first.
)
In ArmVirtualizationPkg/PciHostBridgeDxe we can solve the problem by
working our way downwards from the top of our own aperture.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16906 6f19259b-4bc3-4df7-8a09-765794883524
Currently we allocate IO BARs bottom-up in the
EfiPciHostBridgeAllocateResources phase of the enumeration.
> GCD:AddIoSpace(Base=0000000000000000,Length=0000000000010000)
> GcdIoType = I/O
> Status = Success
> GCDIoType Range
> ========== =================================
> I/O 0000000000000000-000000000000FFFF
Because the IO aperture is based at zero, the first allocation happens to
get the zero address. However, a zero address for a PCI BAR is considered
unmapped; see eg.:
- <http://www.pcisig.com/reflector/msg00459.html>,
- the (new_addr == 0) part in QEMU, pci_bar_address() [hw/pci/pci.c]:
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
last_addr = new_addr + size - 1;
/* Check if 32 bit BAR wraps around explicitly.
* TODO: make priorities correct and remove this work around.
*/
if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX)
{
return PCI_BAR_UNMAPPED;
}
We can avoid this problem by allocating top-down in the IO aperture.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16905 6f19259b-4bc3-4df7-8a09-765794883524
Quite non-intuitively, we must allow guest-side writes to emulated PCI
MMIO regions to go through the CPU cache, otherwise QEMU, whose accesses
always go through the cache, may see stale data in the region.
This change makes no difference for QEMU/TCG, but it is important for
QEMU/KVM, at the moment.
Because gDS->SetMemorySpaceAttributes() is ultimately implemented by
EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() -- see
"MdeModulePkg/Core/Dxe/Gcd/Gcd.c" and "ArmPkg/Drivers/CpuDxe/" -- we add
the CPU architectural protocol to the module's DepEx.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16904 6f19259b-4bc3-4df7-8a09-765794883524
VirtFdtDxe parses the following address space properties from the DTB (and
saves them in PCDs) :
ProcessPciHost: Config[0x3F000000+0x1000000)
Bus[0x0..0xF]
Io[0x0+0x10000)@0x3EFF0000
Mem[0x10000000+0x2EFF0000)@0x0
In order to allow PCI enumeration to allocate IO and MMIO resources from
the above ranges for devices, we must add the ranges to the Global
Coherency Domain.
There are two ways for that:
- building resource descriptor HOBs in the HOB producer phase (basically,
PEI), and letting the DXE core process them,
- calling gDS->AddIoSpace() and gDS->AddMemorySpace() during DXE.
We opt for the second method for simplicity.
In the address space maps, the corresponding ranges change from
"nonexistent" to "IO" and "MMIO", from which the gDS->AllocateIoSpace()
and gDS->AllocateMemorySpace() services can later allocate PCI BARs.
GCD:AddIoSpace(Base=0000000000000000,Length=0000000000010000)
GcdIoType = I/O
Status = Success
GCDIoType Range
========== =================================
-> I/O 0000000000000000-000000000000FFFF
GCD:AddMemorySpace(Base=0000000010000000,Length=000000002EFF0000)
GcdMemoryType = MMIO
Capabilities = 0000000000000001
Status = Success
GCDMemType Range Capabilities Attributes
========== ================================= ================ ================
NonExist 0000000000000000-0000000003FFFFFF 0000000000000000 0000000000000000
MMIO 0000000004000000-0000000007FFFFFF C000000000000001 8000000000000001
NonExist 0000000008000000-000000000900FFFF 0000000000000000 0000000000000000
MMIO 0000000009010000-0000000009010FFF C000000000000001 8000000000000001
NonExist 0000000009011000-000000000FFFFFFF 0000000000000000 0000000000000000
-> MMIO 0000000010000000-000000003EFEFFFF C000000000000001 0000000000000000
NonExist 000000003EFF0000-000000003FFFFFFF 0000000000000000 0000000000000000
SystemMem 0000000040000000-00000000BFFFFFFF 800000000000000F 0000000000000008*
NonExist 00000000C0000000-0000FFFFFFFFFFFF 0000000000000000 0000000000000000
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16903 6f19259b-4bc3-4df7-8a09-765794883524
Set gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize to 16, which determines the
maximum "I/O address width".
This ensures, through the BuildCpuHob() call in
"ArmPkg/Drivers/CpuPei/CpuPei.c", that the inital I/O Space Map will
consist of a 16-bit wide "splittable" entry, when the DXE core starts (see
CoreInitializeGcdServices() in "MdeModulePkg/Core/Dxe/Gcd/Gcd.c"):
GCD:Initial GCD I/O Space Map
GCDIoType Range
========== =================================
NonExist 0000000000000000-000000000000FFFF
Otherwise this range would have size 0, and (since it could not be split)
any gDS->AddIoSpace() calls would fail.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16902 6f19259b-4bc3-4df7-8a09-765794883524
The RootBridgeIoCheckParameter() function currently relies on the range
limit being of the form (2^n - 1). This assumption is not necessarily
true; handle the general case.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16901 6f19259b-4bc3-4df7-8a09-765794883524
There is no IO space on ARM, and there are no special instructions that
access it. QEMU emulates the IO space for PCI devices with a special MMIO
range. We're ready to use it at this point, we just have to switch the
Io(Read|Write)(8|16|32) primitives to their MMIO counterparts, because in
"MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c", the IO primitives
correctly ASSERT (FALSE).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16900 6f19259b-4bc3-4df7-8a09-765794883524
Unlike the one in PcAtChipsetPkg, our PciHostBridgeDxe module must handle
address space translation. IO addresses expressed in the respective
aperture are mapped to a different base in CPU address space.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16899 6f19259b-4bc3-4df7-8a09-765794883524
If VirtFdtDxe found no PCI host in the DTB, then the config space base
address will be left at zero -- the default is set in the DSC --, and we
should exit PciHostBridgeDxe immediately.
This causes gEfiPciRootBridgeIoProtocolGuid not to be installed, which in
turn prevents MdeModulePkg/Bus/Pci/PciBusDxe from binding (see
PciBusDriverBindingSupported()).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16898 6f19259b-4bc3-4df7-8a09-765794883524
Our PciHostBridgeDxe module creates one root bridge on the one and only
host bridge. The resource apertures of the root bridge (bus range, IO
space, MMIO space) are configured with the "mResAperture" array, which at
the moment carries static values inherited from PcAtChipsetPkg.
Set the array as first thing from the PCDs that we parsed from the device
tree.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16897 6f19259b-4bc3-4df7-8a09-765794883524
The Enhanced Configuration Access Mechanism provides access to 4096
register bytes per PCIe B/D/F. The MAX_PCI_REG_ADDRESS macro that we're
changing here is used by RootBridgeIoCheckParameter() for verifying config
space boundaries in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() and
.Write().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16896 6f19259b-4bc3-4df7-8a09-765794883524
Liming Gao
Qiu Shumin
Olivier Martin
Elvin Li
Ronald Cron
Bruce Cran
Laszlo Ersek
Yao, Jiewen