Add Interrupt Vector Flag definitions for Extended Interrupt
Descriptor, and macros to test the flags.
Ref: ACPI specification 6.4.3.6
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
The ProcessorCharacteristics is a UINT16 field, so the
PROCESSOR_CHARACTERISTIC_FLAGS bitfield should be UINT16 too.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
SMBIOS 3.4.0 defines bit 9 of the Type 4 table Processor Characteristics
field to be the ARM64 SoC ID support. Add it to the
PROCESSOR_CHARACTERISTIC_FLAGS struct bitfield.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
In Acpi10.h, EFI_ACPI_DMA_TRANSFER_TYPE_16_BIT is defined as 0x10,
but should be 0x02 per the ACPI Specification.
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2937
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Paul G <paul.grimes@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Add host interface Protocol Type Data Format structure in SmBios.h
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2328
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions
of Compute Express Link Specification register definitions.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of Compute Express Link
Specification Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of upgraded Pci.h.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
The ACPI specification, version 6.3, January 2019,
defines the Named Objects Encoding for FieldElements
in section '20.2.5.2 Named Objects Encoding'.
FieldElements can be one of the following:
NamedField | ReservedField | AccessField |
ExtendedAccessField | ConnectField
Some of these keywords are starting with an opcode,
allowing to identify their type.
E.g.: ReservedField := 0x00 PkgLength
This patch adds these FieldElement opcodes definitions to
the list of AML Opcode definitions.
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
The FUA (Force Unit Access) bit forces data to be written directly to
disk instead of the write cache. This prevents data from being lost if a
shutdown or reset is requested immediately after a SCSI write operation.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Commit c7c964b and dd01704 add header file for FIT table and update
MpInitLib to support FIT based microcode shadow operation. There are
comments that FIT is Intel specific specification instead of industry
standard, which should not be placed in EDK2 MdePkg and UefiCpuPkg.
This patch removes the header file added by c7c964b.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Siyuan Fu <siyuan.fu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
The Platform Communications Channel Table (PCCT) was defined in:
ACPI Specification Version 5.0, Errata A - Published Nov. 13, 2013.
Starting from the Acpi50.h header file, there are definitions
describing the table but a macro with the table's signature is missing.
This patch adds the definition of Platform Communications Channel
Table's signature to the relevant ACPI header files.
Signed-off-by: Krzysztof Koch <krzysztof.koch@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
The header includes Physical Layer PCI Express Extended Capability
definitions based on section 7.7.6 of PCI Express Base Specification 5.0.
Signed-off-by: Felix Polyudov <felixp@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2482
Refer to DSP0134_3.3.0.pdf, there are two additional DWORD added
for type 17. One is "Extended Speed", the other is "Extended
Configured Memory Speed". The lack of these field may cause strange
error in some operating systems.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Fix various typos in comments and documentation.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Antoine Coeur <coeur@gmx.fr>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Philippe Mathieu-Daude <philmd@redhat.com>
Message-Id: <20200207010831.9046-24-philmd@redhat.com>
This patch add FirmwareInterfaceTable.h for the Firmware Interface Table
BIOS specification.
This is to remove future edk2 dependency on edk2-platforms repo. The file
content comes from
edk2-platforms\Silicon\Intel\IntelSiliconPkg\Include\IndustryStandard
BZ link: https://tianocore.acgmultimedia.com/show_bug.cgi?id=2449
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Siyuan Fu <siyuan.fu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The latest TCG PFP specification (TCG PC Client Platform Firmware Profile
Specification, Revision 1.05) added new data structure. For example,
the SPDM device measurement. This patch adds the new content.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Device Control 2 Structure have an issue.
LtrMechanism - there is 2 bits instead of 1.
Signed-off-by: Daniel Pawel Banaszek <daniel.pawel.banaszek@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
As per the Microsoft Debug Port Table 2 (DBG2) documentation, that
can be found online, we are missing 2 serial interface types for
Arm DCC and Bcm2835 (the latter being used with the Raspberry Pi).
These same types are present in DebugPort2Table.h so add them to
SerialPortConsoleRedirectionTable.h too.
Note that we followed the same idiosyncrasies as DebugPort2Table
for naming these new macros.
Signed-off-by: Pete Batard <pete@akeo.ie>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2305
Memory Device (Type 17):
- SMBIOSCR00178: add new memory device type value (HBM) and new form
factor value (Die)
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
The ACPI specification, version 6.3, January 2019,
defines the Named Object Encoding for ExternalOp
in section '20.2.5.2 Named Objects Encoding'.
This patch adds the definition for ExternalOp to
the list of Primary Opcode definitions.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1546
This patch implements the Security Protocol In and Security Protocol Out
commands in UefiScsiLib to prepare support for the Storage Security
Command Protocol.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Christopher J Zurcher <christopher.j.zurcher@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The following two PCI Capability Structure registers are updated as per
the PCI Base Specification Revision 4:-
(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like -
LN system CLS (LnSystemCLS),
10b Tag completer/requester register fields
(TenBitTagCompleterSupported, TenBitTagRequesterSupported),
Emergency power reduction support and initialization requirement
(EmergencyPowerReductionSupported,
EmergencyPowerReductionInitializationRequired),
and FRS support (FrsSupported ).
(2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs
to be upgraded for the -
Emergency power reduction request enabling
(EmergencyPowerReductionRequest), and also the 10b Extended Tag
enabling (TenBitTagRequesterEnable).
The following two are defined as per the PCI Express Base Specification
Revision 2.1:-
(1) Defined macro definitions for all the ranges of Maximum Payload Sizes
and Maximum Read Request Sizes register fields
(2) Defined macro definitions for all the ranges of Completion Timeout
value.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
A previous commit(3cb0a311cb) didn't
clean all IPF contents. So this change removes the rest contents.
https://bugzilla.tianocore.org/show_bug.cgi?id=1560
v2: Withdraw the removal of Mps.h. It is written in Mps.h that
MPS only was included to support Itanium-based platform power on.
But we found MPS is not so relevant to Itanium architecture.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
EFI_RETURNING_FROM_EFI_APPLICATOIN is not correctly spelled,
so now remove it.
https://bugzilla.tianocore.org/show_bug.cgi?id=1368
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The GUID for VIRTUAL_CD_REGION_PERSISTENT was using the closing
square bracket mistakenly.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1099
Add SMBIOS 3.2.0 definitions according to
www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.2.0.pdf.
Processor Information (Type 4):
- SMBIOSCR00163: add socket LGA2066
- SMBIOSCR00173: add Intel Core i9
- SMBIOSCR00176: add new processor sockets
Port Connector Information (Type 8):
- SMBIOSCR00168: add USB Type-C
System Slots (Type 9):
- SMBIOSCR00164: add "unavailable" to current usage field
- SMBIOSCR00167: add support for PCIe bifurcation
Memory Device (Type 17):
- SMBIOSCR00162: add support for NVDIMMs
- SMBIOSCR00166: extend support for NVDIMMs and add support for logical memory type
- SMBIOSCR00172: rename "Configured Memory Clock Speed" to "Configured Memory Speed"
- SMBIOSCR00174: add new memory technology value (Intel Persistent Memory, 3D XPoint)
IPMI Device Information (Type 38):
- SMBIOSCR00171: add SSIF
Management Controller Host Interface (Type 42)
- SMBIOSCR00175: fix structure data parsing issue
V2: Add missing update to MISC_PORT_TYPE and SMBIOS_TABLE_TYPE9.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
1. Do not use tab characters
2. No trailing white space in one line
3. All files must end with CRLF
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Add CapCRBIdleBypass definition to interface ID register. It complies with
existing register
Cc: Long Qin <qin.long@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Long Qin <qin.long@intel.com>
This commit enhances the bitmap fields defined in the IPMI header files,
union types will be used to provide the users with both the individual
bitmap access and the whole byte/word access.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This patch adds the HPET Event Timer Block ID definition that can be
found in the IA-PC HPET Specification, section 3.2.4.
V2:
- Do not change the copyright date as requested.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add link and version info for the referenced spec.
Cc: Jiewen yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
v3: LaneEqualizationControl is changed to be an array.
v2: The structure is updated to include all the fields defined
in the PCI-E specification.
The header includes Physical Layer PCI Express Extended Capability definitions
described in section 7.7.5 of PCI Express Base Specification rev. 4.0.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Felix Polyudov <felixp@ami.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The Type field of EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR should
be UINT8 as ACPI version 6.2 specification.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Support TPM Command cancel if executing command timeouts. Cancel could
happen in long running command case
Cc: Yao Jiewen <jiewen.yao@intel.com>
Cc: Chinnusamy Rajkumar K <rajkumar.k.chinnusamy@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
It was missed to be updated at
SHA-1: 043026ac12.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
For the support of VTd 2.5, add the BIT definition of
DMA_CTRL_PLATFORM_OPT_IN_FLAG
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
PCI_REG_PCIE_SLOT_CONTROL contains a typo. It is defined as:
typedef union {
struct {
UINT32 AttentionButtonPressed : 1;
UINT32 ...
...
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
The bit field data type should be UINT16 instead of UINT32,
results sizeof (PCI_REG_PCIE_SLOT_CONTROL) equals to 4 instead of 2.
Because this structure is used in PCI_CAPABILITY_PCIEXP as below:
typedef struct {
...
PCI_REG_PCIE_SLOT_CONTROL SlotControl;
PCI_REG_PCIE_SLOT_STATUS SlotStatus;
} PCI_CAPABILITY_PCIEXP;
It cause the OFFSET_OF (PCI_CAPABILITY_PCIEXP, SlotStatus) equal
to a wrong value.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Revision 2.2 of the PCI Spec defines Capability IDs 0 through 6,
inclusive, in Appendix H. It reserves IDs 7 through 255.
Revision 2.3 of the PCI Spec adds Capability IDs 7 through 0xC, inclusive,
in Appendix H. Capability ID 9 stands for "Vendor Specific".
Add the EFI_PCI_CAPABILITY_ID_VENDOR macro and the
EFI_PCI_CAPABILITY_VENDOR_HDR structure type to MdePkg/IndustryStandard,
in order to describe this capability header.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This patch adds a few more UDF volume structures in order to detect an
UDF file system which is supported by current EDK2 UDF file system
implementation in Partition driver.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Paulo Alcantara <pcacjr@zytor.com>
Build-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Tested-by: Hao Wu <hao.a.wu@intel.com>
Build-tested-by: Star Zeng <star.zeng@intel.com>
Build-tested-by: Paulo Alcantara <paulo@hp.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This patch adds basic volume structure definitions necessary to identify
a valid UDF file system on a block device, as specified by OSTA
Universal Disk Format Specification 2.60.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Paulo Alcantara <pcacjr@zytor.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
The patch adds new macro PCI_ECAM_ADDRESS into PciExpress21.h,
to align to the PCIE spec, and also update PciExpressLib.h to
redirect PCI_EXPRESS_LIB_ADDRESS to the new macro.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The definition for 1.1a has no difference with 1.0.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This updates the IORT header to include the definitions that were added
in revision C of the IORT spec that was made public recently.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This adds #defines and struct typedefs for the various node types in
the ACPI 6.0 IO Remapping Table (IORT).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jiewen Yao <yiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=363
The definition name for ACPI IO Remapping Table signature is incorrect
in Acpi60.h and Acpi61.h as below:
EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_SIGNATURE
EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_SIGNATURE
The name should be changed to
EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE
EFI_ACPI_6_1_IO_REMAPPING_TABLE_SIGNATURE
The comments
///
/// "IORT" Interrupt Source Override
///
will be also changed to
///
/// "IORT" I/O Remapping Table
///
Cc: Alexei Fedorov <Alexei.Fedorov@arm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
DEVICE_ID_NOCARE is defined as 0xFFFF but Spec says (UINT64) -1
should be used to match any VendorId/DeviceId/RevisionId/
SubsystemVendorId/SubsystemDeviceId.
PCI_BAR_OLD_ALIGN/PCI_BAR_EVEN_ALIGN/PCI_BAR_SQUAD_ALIGN/
PCI_BAR_DQUAD_ALIGN are defined but Spec doesn't have such
definitions.
PCI_BAR_ALL is defined as 0xFF but Spec says (UINT64)-1 should be
used to match all BARs.
PCI_ACPI_UNUSED and PCI_BAR_NOCHANGE are defined as 0 which
compliant with Spec but the name is too general and causes confusing.
IncompatiblePciDeviceSupport could directly use 0.
All of the above macros are marked as deprecated.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=340
TPM Device (Type 43) definition has been added at
713e4b007c.
This patch is to add definitions for below items.
• BIOS Information (Type 0):
– Add new entry for extended BIOS ROM size
• System Enclosure or Chassis (Type 3):
– Add new chassis types: IoT Gateway and Embedded PC
– Add new chassis types: Mini PC and Stick PC
• Processor Information (Type 4):
– Add Intel Core m3 m5 m7 processors
– Add processor socket AM4
– Add processor socket LGA1151
– Add processor socket BGA1356, BGA1440, BGA1515
– Add AMD Opteron A-Series processor
– Add processor socket LGA3647-1
– Add processor socket SP3 Processors
– Add families for ARMv7 and ARMv8
– Add family for AMD Opteron(TM) X3000 Series APU
• Cache Information (Type 7):
– Extend to support Cache sizes >2047 MB
• System Slots (Type 9):
– Add Mini PCIe support
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Starting with SMBIOS spec version 2.7, Type 3 added SKU Number.
SKU Number is at a variable offset (depends on count and length of Contained Elements), so cannot add SKU Number to the SMBIOS_TABLE_TYPE3 structure.
Adding comments to explain how to get SKU Number.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <chrisp@hpe.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Added definitions for the new SMBIOS Type 43 record.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Augustine Linson P <linson.augustine@hpe.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Fix incompatible change. Some modules are still referencing old definition.
Cc: Star Zeng <star.zeng@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
Update TPM2 ACPI Table revision to 4. New version & data structure is
defined in TCG ACPI Spec 00.37
Cc: Star Zeng <star.zeng@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
This path is used to standardize TLS definitions from related
RFCs. Including TLS Cipher Suites, TLS Version, TLS Content Type
and TLS Record Header, etc.
Cc: Long Qin <qin.long@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Thomas Palmer <thomas.palmer@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=201
In V3, Use Odt to replace ODT, Cke to replace CKE, Id to replace ID,
and Cl to replace CL in structure field name.
In V2, separate DDR3, DDR4 and LPDDR definition into the different files;
use the different SPD prefix as structure definitions for each SPD type.
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
The "Pci22.h" header file defines the macro EFI_PCI_CAPABILITY_ID_HOTPLUG
with value 0x06. According to all of:
- later parts of the same header file,
- Appendix H ("Capability IDs") of the PCI Local Bus Specification
Revision 2.3,
- and Chapter 2 ("Capability IDs") of the PCI Code and ID Assignment
Specification Revision 0.9,
0x06 means "CompactPCI Hot Swap". It does not mean "PCI Hot-Plug": that
capability is described by ID 0x0C:
0Ch PCI Hot-Plug -- This Capability ID indicates that the associated
device conforms to the Standard Hot-Plug Controller model.
Therefore EFI_PCI_CAPABILITY_ID_HOTPLUG is arguably a misnomer. PciBusDxe
(mis-)uses EFI_PCI_CAPABILITY_ID_HOTPLUG in the IsSHPC() helper function
to identify PCI Hot-Plug capability.
In order to preserve compatibility with existent code, leave
EFI_PCI_CAPABILITY_ID_HOTPLUG alone, and introduce
EFI_PCI_CAPABILITY_ID_SHPC with the right ID value.
Cc: "Johnson, Brian J." <bjohnson@sgi.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
Sami Mujawar
Rebecca Cran
Abner Chang
Wang, Sanyo
Paul
Javeed, Ashraf
Wasim Khan
Pierre Gondois
Zurcher, Christopher J
Siyuan Fu
Krzysztof Koch
Felix Polyudov
Matthew Carlson
Antoine Coeur
Jiewen Yao
Daniel Pawel Banaszek
Pete Batard
Gao, Zhichao
Shenglei Zhang
Michael D Kinney
Bret Barkelew
Zhang, Chao B
Gary Lin
Star Zeng
Liming Gao
Hao Wu
Marvin.Haeuser@outlook.com
Eric Dong
Jiaxin Wu
Heyi Guo
Ming Huang
Ruiyu Ni
Laszlo Ersek
Paulo Alcantara
Ard Biesheuvel
Chris Phillips
Linson Augustine
Giri P Mudusuru
Feng Tian