'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only
be invoked from EL2.
The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates
the TLBs of the current VMID.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
Add a new instance of DevicePathLib which tries to locate the protocol and if it's not found, it uses the internal functions.
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14504 6f19259b-4bc3-4df7-8a09-765794883524
Modifies StdLib/StdLib.inc to include the ARM CompilerIntrinsicsLib when building for Aarch64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed by: Daryl McDaniel <daryl.mcdaniel@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14499 6f19259b-4bc3-4df7-8a09-765794883524
This is based on MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c.
Previously we would run using page tables built into the
firmware device.
If a flash memory is available, it is unsafe for the page
tables to be stored in memory since the processor may try
to write to the page table data structures.
Additionally, when KVM ROM support is enabled for the
firmware device, then PEI fails to boot when the page
tables are in the firmware device.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14494 6f19259b-4bc3-4df7-8a09-765794883524
When the PM base address was moved from 0x400 to 0xb000, this
code was missed. This prevented shutdown's via the UEFI system
call from working. (For example, at the EFI shell prompt: reset -s)
We now use gUefiOvmfPkgTokenSpaceGuid.PcdAcpiPmBaseAddress
which is currently set at 0xb000.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14492 6f19259b-4bc3-4df7-8a09-765794883524
Some missing files from the initial AArch64 commit.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14488 6f19259b-4bc3-4df7-8a09-765794883524
the PCI Bus driver through the function call NotifyPhase().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14483 6f19259b-4bc3-4df7-8a09-765794883524
while MonthNo is the month of the year, so tm_mon should be MonthNo-1.
Similarly, tm_mday is the day of the month, and DayNo is the number
of days since the first day of the month. Assigning DayNo+1 to
tm_mday to fit the definition.
This commit also corrected miscalculated MonthNo and DayNo for the
first day of the month. (Thanks to Laszlo Ersek!)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Ching-Pang Lin <glin@suse.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Long Qin <qin.long@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14481 6f19259b-4bc3-4df7-8a09-765794883524
The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first
registers of the GIC CPU Target Registers.
The first GIC Distributor Target registers correspond to the SGIs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
This function is exposed by the MemoryAllocationLib header.
A dummy FreePages() function has been added to fix modules depending on
this library and this function.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14478 6f19259b-4bc3-4df7-8a09-765794883524
The idea is to remove the PCD PcdGicPrimaryCoreId to make the port easier (and also to allow changing
the primary boot CPU without adding more platform specific code to UEFI).
There is a risk the mailboxes contain garbage at boot time. But it should be easy enough to clear the
mailboxes when starting UEFI to workaround this limitation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14477 6f19259b-4bc3-4df7-8a09-765794883524
Route both the setting and restoring of cacheability through DXE Services/GCD
and stop using the CPU AP directly.
The patch also removes all references to the CPU AP which eliminates the need
for a library constructor.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Senthil Ramakrishnan <senthil.ramakrishnan@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14468 6f19259b-4bc3-4df7-8a09-765794883524
Harry Liebel
Liming Gao
Eric Dong
Olivier Martin
Ruiyu Ni
Fu Siyuan
Jordan Justen
Jaben Carsey
Gary Ching-Pang Lin
Eugene Cohen