We need to add EFIAPI for all interface service including library API.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leo Duran <leo.duran@amd.com>
Cc: Michael Kinney <Michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Leo Duran <leo.duran@amd.com>
GetProcessorLocation() is too generic and will conflict with the API defined in
Galileo Board Software Package v1.0.0.
This update is just to rename GetProcessorLocation() to one specific name
GetProcessorLocationByApicId().
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leo Duran <leo.duran@amd.com>
Cc: Michael Kinney <Michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Leo Duran <leo.duran@amd.com>
1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.
Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.
v5:
1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
The LocalApicLib does not provide a function to manage the state of the
Local APIC SoftwareEnable bit in the Spurious Vector register. There
are cases where this bit needs to be managed without side effects to.
other Local APIC registers. One use case is in the DebugAgent in the
SourceLevelDebugPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18711 6f19259b-4bc3-4df7-8a09-765794883524
Move CPUID related defines from LocalApic.h to Cpuid.h
Update LocalApicLib instances to include Cpuid.h
Update CpuMpPei module to include Cpuid.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18633 6f19259b-4bc3-4df7-8a09-765794883524
Add an ASSERT in GetApicTimerState() to check if the local APIC is
software enabled.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18595 6f19259b-4bc3-4df7-8a09-765794883524
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17217 6f19259b-4bc3-4df7-8a09-765794883524
2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler.
3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com>
Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524
Its default value is 10 millisecond per IA32 manual.
Platform could customize this PCD value for performance requirement.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15650 6f19259b-4bc3-4df7-8a09-765794883524
2. Read CPU APIC ID from CPUID leaf B in case CPU Init APIC ID is larger 255 in XAPIC mode.
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14674 6f19259b-4bc3-4df7-8a09-765794883524
2. Updated Local APIC library instances to get Local APIC base Address by invoking GetLocalApicBaseAddress() instead of by PCD PcdCpuLocalApicBaseAddress.
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com>
Reviewed-by: Rui Sun <rui.sun@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13668 6f19259b-4bc3-4df7-8a09-765794883524
Use the library functions for shift operations in BaseLib for a 64-bit integer where the code is shared for 32-bit and 64-bit.
Defining bitfields in structures with > 32 bits will cause these types of issues on IA32 builds. So the largest bitfield should be type UINT32 with a max size of :32.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10983 6f19259b-4bc3-4df7-8a09-765794883524
Jeff Fan
Leo Duran
Michael Kinney
Hao Wu
vanjeff
mdkinney
rsun3