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This new PCD is used to specify the AP C-state value by MWAIT instruction. More deeper C-state means more longer latency time when APs exiting from MWAIT state. Platforms need to balance the performance and power saving to find the proper C-state for APs. Also, some processor may not ready for the deepest C-state at the beginning. Platform also could choose the proper chance to place AP into the deeper C-state by set this PCD before hand-off to OS. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19342 6f19259b-4bc3-4df7-8a09-765794883524