When building PIE (ET_DYN) executables, an additional RELA section is
emitted (in addition to the per-section .rela.text and .rela.data sections)
that is intended to be resolved at runtime by a ET_DYN compatible loader.
At the moment, due to the fact that we don't support GOT based relocations,
this dynamic RELA section only contains relocations that are redundant,
i.e., each R_xxx_RELATIVE relocation it contains duplicates a R_xxx_xx64
relocation appearing in .rela.text or .rela.data, and so we can simply
ignore this section (and we already ignore it in practice due to the fact
that it points to the NULL section, which has the SHF_ALLOC bit cleared).
For example,
Section Headers:
[Nr] Name Type Address Offset
Size EntSize Flags Link Info Align
[ 0] NULL 0000000000000000 00000000
0000000000000000 0000000000000000 0 0 0
[ 1] .text PROGBITS 0000000000000240 000000c0
000000000000427c 0000000000000008 AX 0 0 64
[ 2] .rela.text RELA 0000000000000000 00009310
0000000000001bf0 0000000000000018 I 7 1 8
[ 3] .data PROGBITS 00000000000044c0 00004340
00000000000046d0 0000000000000000 WA 0 0 64
[ 4] .rela.data RELA 0000000000000000 0000af00
0000000000000600 0000000000000018 I 7 3 8
[ 5] .rela RELA 0000000000008bc0 00008a10
0000000000000600 0000000000000018 0 0 8
[ 6] .shstrtab STRTAB 0000000000000000 0000b500
0000000000000037 0000000000000000 0 0 1
[ 7] .symtab SYMTAB 0000000000000000 00009010
0000000000000210 0000000000000018 8 17 8
[ 8] .strtab STRTAB 0000000000000000 00009220
00000000000000eb 0000000000000000 0 0 1
Relocation section '.rela.data' at offset 0xaf00 contains 64 entries:
Offset Info Type Sym. Value Sym. Name + Addend
000000004800 000100000001 R_X86_64_64 0000000000000240 .text + 3f5b
000000004808 000100000001 R_X86_64_64 0000000000000240 .text + 3f63
000000004810 000100000001 R_X86_64_64 0000000000000240 .text + 3f79
000000004818 000100000001 R_X86_64_64 0000000000000240 .text + 3f90
000000004820 000100000001 R_X86_64_64 0000000000000240 .text + 3fa6
...
Relocation section '.rela' at offset 0x8a10 contains 64 entries:
Offset Info Type Sym. Value Sym. Name + Addend
000000004800 000000000008 R_X86_64_RELATIVE 419b
000000004808 000000000008 R_X86_64_RELATIVE 41a3
000000004810 000000000008 R_X86_64_RELATIVE 41b9
000000004818 000000000008 R_X86_64_RELATIVE 41d0
000000004820 000000000008 R_X86_64_RELATIVE 41e6
000000004828 000000000008 R_X86_64_RELATIVE 41ff
...
Note that GOT based relocations result in entries that *only* appear in the
dynamic .rela section and not in .rela.text or .rela.data. This means two
things if we intend to add support for GOT based relocations:
- we must check that a dynamic RELA section exists;
- we must filter out duplicates between .rela and .rela.xxx, to prevent
emitting duplicate fixups into the PE/COFF .reloc section.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
We have added a new policy to get default value for question:
get default from other default id if current default is not specified.
But when getting default value for checkbox, if the default
flag is not set, it will set the default value to FALSE for checkbox.
This behavior in checkbox conflicts with the new added policy,
so now we move this behavior to the end of getting default form other
default id.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
1) Fixed the VBT size from 0x1C00(7KB) to 0x1800(6KB) and typos, indentation
2) Updated offsets in hex values and offset from start of OPREGION
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
we need to locate the FSP Info Header before the stack is initialized to
access the cfg region for any UPD. Hence adding the
AsmGetFspInfoHeaderNoStack function to support it.
Note: This function is there in IntelFspPkg but got removed in IntelFsp2Pkg
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Satya Yarlagadda <satya.p.yarlagadda@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
add Pkcs7Sign.exe and related pem file into BinaryFiles.txt for build
server to automatically build the binary win32 files.
Cc: Liming Gao <liming.gao@intel.com>
CC: Erik Bjorge <erik.c.bjorge@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
in last commit 91ae29, it missed to add the
EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER for the auth FMP capsule.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The .rtf files in BaseTools/UserManuals still tell users to Report bugs
to sourceforge mail address. Since we no longer use the sourceforge
mailing lists we should update it.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit removes the internal implementation of the function
InternalIsZeroBuffer(). Instead, it will use the API IsZeroBuffer() from
BaseMemoryLib in MdePkg.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add the implementation of API IsZeroBuffer() via assembly in
BaseMemoryLibSse2.
The assembly codes use SSE2 XMM registers and related instructions.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add the implementation of API IsZeroBuffer() via assembly for the
following library instances:
BaseMemoryLibMmx
BaseMemoryLibOptDxe
BaseMemoryLibOptPei
BaseMemoryLibRepStr
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add the implementation of API IsZeroBuffer() via C language for the
following library instances:
BaseMemoryLib
PeiMemoryLib
UefiMemoryLib
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
The CLANG38 toolchain creates a PIE binary at link time. This is
necessary since the LTO code generation may otherwise result in
code that cannot execute correctly when loaded above 2 GB.
PIE executables contain a RELA section consisting of dynamic
relocation entries that are intended for consumption by the loader
at runtime. For this reason, it has the SHF_ALLOC attribute set by
default, and will be identified by GenFw as a section that needs to
be copied into the PE/COFF binary, resulting in waste of space since
the PE/COFF loader does not use this data at all.
So mark the RELA section as informational: this will prevent the
linker from setting the SHF_ALLOC attribute, causing GenFw to
ignore it.
DxeCore.efi before:
Detected 'X64' type PE/COFF image consisting of 3 sections
Section alignment: 0x40
File alignment: 0x40
Section '.text' @ 0x00000240
File offset: 0x240
Virtual size: 0x21000
Raw size: 0x21000
Section '.data' @ 0x00021240
File offset: 0x21240
Virtual size: 0x3640
Raw size: 0x3640
Section '.reloc' @ 0x00024880
File offset: 0x24880
Virtual size: 0x280
Raw size: 0x280
DxeCore.efi after:
Detected 'X64' type PE/COFF image consisting of 3 sections
Section alignment: 0x40
File alignment: 0x40
Section '.text' @ 0x00000240
File offset: 0x240
Virtual size: 0x1f440
Raw size: 0x1f440
Section '.data' @ 0x0001f680
File offset: 0x1f680
Virtual size: 0x3640
Raw size: 0x3640
Section '.reloc' @ 0x00022cc0
File offset: 0x22cc0
Virtual size: 0x280
Raw size: 0x280
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Added missing dependency of FileExplorerLib, which was causing
build error for ArmVirtXen, due to inclusion of ramdisk support.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
If PE image has no relocation section, and has not set RELOCS_STRIPPED,
after it is converted to TE image, GenFw will set its relocation section
VirtualAddress to non-zero address, and keep Size value as Zero. MdePkg
BasePeCoffLib applied this rule to get RelocationsStripped attribute. But,
it is missing in BaseTools BasePeCoffLib.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Adds the RAMDisk support to ArmVirtPkg platforms.
This patch actually ports OvmfPkg commit 259d87146b to
ArmVirtPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Since ArmVirt.dsc.inc is included in all the ArmVirt dsc files,
move inclusion of AcpiTableDxe.inf to ArmVirt.dsc.inc.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Vikas C Sajjan <vikas.cha.sajjan@hpe.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Current BaseTools query the BuildOptions not cover the case that use
'COMMON' as CodeBase, while DSC spec allow this usage. This Patch add
support for such 'common.DXE_RUNTIME_DRIVER' as the Scope2 in the query
Condition.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Kurt Kennett <Kurt.Kennett@microsoft.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Current BaseTools cannot generate EFI_FIRMWARE_IMAGE_AUTHENTICATION
for FMP capsule. this patch fix it by FDF spec's update to add the
definition for CERTIFICATE_GUID and MONOTONIC_COUNT. BaseTools call
the tool by CERTIFICATE_GUID to generate the certdata and fill the header
info.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
the EFI_FIRMWARE_IMAGE_AUTHENTICATION struct require the AuthInfo which
is a signature across the image data and the Monotonic Count value, so we
add the new option to support Monotonic count.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Provide the PKCS7 Tool to support the CertType - EFI_CERT_TYPE_PKCS7_GUID,
then user can use this tool to add EFI_FIRMWARE_IMAGE_AUTHENTICATION
for a binary.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
CLANG38 build fail after CC_FLAG is added in the link rule.
This failure is because the CLANG38 enable the LTO through LLVMgold.so
linker plugin, but the LLVMgold.so plugin cannot accept the clang -Oz
CC flag as build option. After CC_FLAG is added in the link rule,
the LLVMgold.so plugin reports linking error. LLVMgold.so only accept
-O0 ~ -O3, and you can see it in the LLVM gold plugin source code
in below:
http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_380/final/tools/gold/
gold-plugin.cpp line173:
if (opt[1] < '0' || opt[1] > '3')
message(LDPL_FATAL, "Optimization level must be between 0 and 3");
Add -O3 in the *_CLANG38_*_DLINK2_FLAGS to override the -Oz flag in
*_CLANG38_*_CC_FLAGS to pass LLVMgold.so linking.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Steven Shi <steven.shi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Add CONF_PATH env check. First priority is user set the conf dir by
--conf option, then the CONF_PATH env, the last one is the standard
WORKSPACE(PACKAGE_PATH)/Conf.
Also print the conf path directory in the build log.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
*v2: update the commit log and refine the code comments.
There are three kinds of IKE Exchange process:
#1. Initial Exchange
#2. CREATE_CHILD_SA_Exchange
#3. Information Exchange
The IKE header "FLAG" update is incorrect in #2 and #3 exchange,
which may cause the continue session failure. This patch is used
to correct the updates of IKE header "FLAG" according the RFC4306
section 3.1.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
*v2: update the commit log.
IKE Initial Exchange message should cover below process:
Initiator Responder
Message1 HDR,SAil,KEi,Ni ------>
Message2 <------ HDR,SArl,KEr,Nr,[CERTREQ]
Message3 HDR,SK{} ------>
Message4 <------ HDR,SK{}
If Initial Exchange message is initiated by Linux IKE, it works well.
But the failure will happen if it's initiated by UEFI IKE. This issue
is caused by the no status check of NotifyCookiePayload.
While parsing the IKEv2 packet for IKE_SA_INIT exchange, if the packet
doesn't contain COOKIE Notify payload, EFI_INVALID_PARAMETER will be
returned from Ikev2ParserNotifyCookiePayload(). Current implementation
return this error status directly, then the session will be broken. The
correct behavior should check this status. If no COOKIE Notify payload,
initiator don't need to retry the IKE_SA_INIT.
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Zhang Lubo <lubo.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Section alignment of .data in GCC49 and GCC5 are 0x40
rather than 0x20 in GCC48 and below.
This causes a hang in PeiCore.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
MpInitLib is consumed by CpuDxe
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
Reviewed by: Maurice Ma <maurice.ma@intel.com>
IpSb->Reconfig should not be set to TRUE to focal the reconfiguration
during the policy changes from Static to DHCP. It's redundancy because
the default router table and default addresses have been freed ahead (
Detailed see Ip4Config2OnPolicyChanged() function). Otherwise, the
potential failure will appear if UseDefaultAddress configured. Reproduce
steps see below:
#1. Set policy to DHCP.
#2. If DHCP process is not complete yet, then run one APP to invoke UDP4
Configure with "UseDefaultAddress = TRUE" (loop to call UDP4 Configure
until Ip4Mode.IsConfigured changes to TRUE).
#3. Even DHCP succeed but Ip4Mode.IsConfigured flag never set to TRUE
Concrete analysis is as follows:
In #1, the policy will be set to DHCP, and then Ip4Config2OnPolicyChanged()
will be called. In this function, if "IpSb->Reconfig" flag is set to TRUE,
the original "IpSb->DefaultInterface" will be abandoned/freed once the
DHCP process finished.
In #2, UDP4 Configure with "UseDefaultAddress = TRUE" is called, that means
the default interface (IpSb->DefaultInterface) will be selected as current
instance's interface.
In #3, when DHCP process finished, the original DefaultInterface will be
abandoned/freed because "IpSb->Reconfig" flag is true. Meanwhile, one new
interface is assigned to "IpSb->DefaultInterface". This new interface is
different to the original one assigned to the UDP4 Configured instance. So,
even DHCP process succeed, the up caller will never have the chance to get
it's truly status.
Cc: Cohen Eugene <eugene@hp.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Tested-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
The bug is caused by using already freed memory.
If there is already an attempt and execute
'reconnect -r' command, all the AttemptConfig structure
will be freed, but the mCallbackInfo->Current is not
configured as null and this pointer will be used again in
IScsiFormExtractConfig.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
The RSDT is only used when the bios need to support ACPI 1.0
version. When change PcdAcpiExposedTableVersions to 0x3C, it
will not support ACPI 1.0. The default is 0x3E.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
The RSDT is only used when the bios need to support ACPI 1.0
version. When change PcdAcpiExposedTableVersions to 0x3C, it
will not support ACPI 1.0. The default is 0x3E.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Compute the number of ticks to wait to measure TSC frequency.
Instead of (ACPI_TIMER_FREQUENCY / 10000) = 357 and 357 * 10000 = 3570000,
use 363 * 9861 = 3579543 Hz which is within 2 Hz of ACPI_TIMER_FREQUENCY.
363 counts is a calibration time of 101.4 uS.
The idea comes from Michael and Paolo.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Paul A Lohr <paul.a.lohr@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
PiSmmCpuDxeSmm driver's entry point will get some PCDs supported dynamic type.
In case those PCDs are set as DynamicHii type in platform DSC File, it implies
that EFI Variable Arch protocol is required.
This fix is to add gEfiVariableArchProtocolGuid dependency on PiSmmCpuDxeSmm
driver to make sure those DynamicHii PCDs could be read correctly.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
v5:
If PcdCpuMaxLogicalProcessorNumber is set to 1 on UP system,
MpInitLibInitialize() will be invoked. This is one bug, we need to
call MpInitLibInitialize() always and get the BSP information.
Just to remove PcdCpuMaxLogicalProcessorNumber() consuming from this
driver.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Consume MP Initialize library to produce CPU MP Protocol services to simply the
code.
v4:
1. Update CpuDxe.c file header to mention it produces CPU Arch protocol.
2. Update BistData type from UINT32 to EFI_HEALTH_FLAG.
3. Move some header location from CpuMp.h to CpuDxe.h.
v3:
1. Move the code Consume MpInitLib APIs to produce CPU MP Protocol from patch
#40 to this patch.
2. Add DxeMpInitLib.inf in DSC file
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Consume MP initialize library to produce CPU MP PPI, it could simply the code.
Add STATIC for some internal functions to avoid build issue with the same
functions name in PeiMpInit instance. They will be removed by the next patch.
v4:
1. Update BistData type from UINT32 to EFI_HEALTH_FLAGS.
v3:
1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP
2. Add PeiMpInitLib.inf in DSC file
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
This update is for CpuDxe consuming MP Initialize library.
v5:
1. Update Quark DSC files to add PeiMpInitLib.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Ard Biesheuvel
Liming Gao
Mudusuru, Giri P
Yarlagadda, Satya P
Yonghong Zhu
Hao Wu
Vikas C Sajjan
Jeff Fan
Shi, Steven
Jiaxin Wu
Prince Agyeman
Zhang Lubo
Star Zeng