To convert these files I ran:
$ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
Add new API MtrrSetMemoryAttributeInMtrrSettings() in MtrrLib. Platform could
use this API to set MTRR setting into local MTRR settings buffer instead of
MTRRs. At last, platform could use MtrrSetAllMtrrs() to set the MTRR settings
into MTRRs totally. It could improve MTRRs programming performance obviously,
specially when platform is going to program a set of MTRRs.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19162 6f19259b-4bc3-4df7-8a09-765794883524
MtrrDebugPrintAllMtrrsWorker() provides the capability to dump the MTRR setting
from MTRRs or the input MTRR settings buffer.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19161 6f19259b-4bc3-4df7-8a09-765794883524
When MtrrSetMemoryAttribute() programs variable MTRRs, it may disable/enable
cache and disable/enable MTRRs several times. This updating tries to do
operation in local variable and does the hardware initialization one time only.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19158 6f19259b-4bc3-4df7-8a09-765794883524
When MtrrSetMemoryAttribute() programs fixed MTRRs, it may disable/enable cache
and disable/enable MTRRs several times. This updating tries to do operation in
local variable and does the hardware initialization one time only.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19157 6f19259b-4bc3-4df7-8a09-765794883524
Add function to shadow the content of variable MTRRs into an internal array:
VariableMtrr. And used MtrrGetMemoryAttributeInVariableMtrrWorker() in other
functions.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19156 6f19259b-4bc3-4df7-8a09-765794883524
Try to make use of worker functions to get MTRRs count. It could avoid invoking
IsMtrrSupported() for many times.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19155 6f19259b-4bc3-4df7-8a09-765794883524
Only adjust functions order and there is no any real functionality impact.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19154 6f19259b-4bc3-4df7-8a09-765794883524
Abstract some worker functions not to invoke IsMtrrSupported(). They could be
used by other functions to reduce the number of invoking times on
IsMtrrSupported().
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19153 6f19259b-4bc3-4df7-8a09-765794883524
Current MtrrLib reserves 2 variable MTRRs for some legacy OS boot (CSM boots)
may require some MTRRs to be reserved for OS use. But UEFI OS boot will not use
MTRRs.
Per Scott's suggestion in
link: http://article.gmane.org/gmane.comp.bios.edk2.devel/4099
Add one PCD PcdCpuNumberOfReservedVariableMtrrs to specify the number of
variable MTRRs reserved for OS use. Setting its default value to 2 is for
back-compatibility.
Cc: Scott Duplichan <scott@notabs.org>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Suggested-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19151 6f19259b-4bc3-4df7-8a09-765794883524
Add NULL func for 2 new APIs in SmmCpuFeaturesLib.
SmmCpuFeaturesCompleteSmmReadyToLock() is a hook point to allow
CPU specific code to do more registers setting after
the gEfiSmmReadyToLockProtocolGuid notification is completely processed.
Add SmmCpuFeaturesCompleteSmmReadyToLock() to PerformRemainingTasks() and PerformPreTasks().
SmmCpuFeaturesAllocatePageTableMemory() is an API to allow
CPU to allocate a specific region for storing page tables.
All page table allocation will use AllocatePageTableMemory().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18958 6f19259b-4bc3-4df7-8a09-765794883524
Bit SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP is defined in SDM.
If set to 1 indicates that the SMM code access restriction is supported and the
MSR_SMM_FEATURE_CONTROL is supported.
If this bit is not set, we needn't to access register SmmFetureControl.
Otherwise, #GP exception may happen.
We need to check if SmmFeatureControl support or not by checking
SMM_Code_Access_Chk (SMM-RO) in MSR_SMM_MCA_CAP.
Because MSR_SMM_MCA_CAP is SMM-RO register, we should move this check from
SmmCpuFeaturesLibConstructor (non-SMM) to SmmCpuFeaturesInitializeProcessor
(SMM).
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18906 6f19259b-4bc3-4df7-8a09-765794883524
The LocalApicLib does not provide a function to manage the state of the
Local APIC SoftwareEnable bit in the Spurious Vector register. There
are cases where this bit needs to be managed without side effects to.
other Local APIC registers. One use case is in the DebugAgent in the
SourceLevelDebugPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18711 6f19259b-4bc3-4df7-8a09-765794883524
Add support for the reading and writing MSR_SMM_FEATURE_CONTROL
through the SmmCpuFeaturesIsSmmRegisterSupported(),
SmmCpuFeaturesGetSmmRegister(), and SmmCpuFeaturesSetSmmRegister()
functions. This MSR is supported if the Family/Model is 06_3C,
06_45, or 06_46.
Cc: "Yao, Jiewen" <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: "Yao, Jiewen" <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18690 6f19259b-4bc3-4df7-8a09-765794883524
Add SmmCpuPlatformHookLib that provides platform specific functions
that are used to initialize SMM and process SMIs. A Null instance
of this library is provided that should work for most platforms.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18639 6f19259b-4bc3-4df7-8a09-765794883524
Add SmmCpuFeaturesLib that provides CPU specific functions that are
used to initialize SMM and process SMIs. A functional implementation
of this library class is provided that is based on the
Intel(R) 64 and IA-32 Architectures Software Developer's Manual
[jeff.fan@intel.com: Fix code style issues reported by ECC]
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18638 6f19259b-4bc3-4df7-8a09-765794883524
Add PlatformSecLib class and PlatformSecLibNull instance
that is used by the SecCore. PlatformSecLibNull should
not be used in a platform build. Instead, it should be
used as a template for implementing a platform specific
instance of the PlatformSecLib library class.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18635 6f19259b-4bc3-4df7-8a09-765794883524
Move CPUID related defines from LocalApic.h to Cpuid.h
Update LocalApicLib instances to include Cpuid.h
Update CpuMpPei module to include Cpuid.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18633 6f19259b-4bc3-4df7-8a09-765794883524
Add an ASSERT in GetApicTimerState() to check if the local APIC is
software enabled.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18595 6f19259b-4bc3-4df7-8a09-765794883524
When the local APIC is not configurated properly, function
GetApicTimerInitCount() in LocalApicLib may return zero, which will lead
to a divide by zero exception in SecPeiDxeTimerLibUefiCpu.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18594 6f19259b-4bc3-4df7-8a09-765794883524
Per IA32 SDM, if CPUID.80000008H is not available, software may assume that the
processor supports a 36-bit physical address size.
However, for such old processors (For example, Quark processor),
MtrrValidBitsMask and MtrrValidAddressMask values are reverted and wrong in
MtrrLib. MtrrValidBitsMask should be 0xFFFFFFFFFULL and MtrrValidAddressMask
should be 0xFFFFFF000ULL.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18396 6f19259b-4bc3-4df7-8a09-765794883524
Add exception type decoder to print exception name string beside print
exception type value. The exception names are from IA32 SDM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17877 6f19259b-4bc3-4df7-8a09-765794883524
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions.
Do not enable those features in CR4 if they are not supported.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17221 6f19259b-4bc3-4df7-8a09-765794883524
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17217 6f19259b-4bc3-4df7-8a09-765794883524
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17216 6f19259b-4bc3-4df7-8a09-765794883524
Make code consistence between ASM and S files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16530 6f19259b-4bc3-4df7-8a09-765794883524
.S assembler files must be AT&T syntax ones. So Intel syntax mnemonic is not good. Discovered by clang integrated assembler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Nikolai Saoukh <nms@otdel-1.org>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16100 6f19259b-4bc3-4df7-8a09-765794883524
.S assembler files must be AT&T syntax ones. So Intel syntax mnemonic is not good. Discovered by clang integrated assembler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Nikolai Saoukh <nms@otdel-1.org>
Reviewed-by: Andrew Fish <afish@apple.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16098 6f19259b-4bc3-4df7-8a09-765794883524
CpuExceptionHandlerLib has code that contains absolute relocations, not supported by
Xcode for X64, and it then copies this code to an alternate location in memory. It is
very hard to write IP relative self-modifiying code. I had to update AsmVectorNumFixup()
to also patch in the absolute addressess after the code was copied.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Anderw Fish <afish@apple.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16068 6f19259b-4bc3-4df7-8a09-765794883524
Module UNI and Package UNI files are not DOS format. Convert them to DOS format.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gao, Liming <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16047 6f19259b-4bc3-4df7-8a09-765794883524
2. Add MODULE_UNI_FILE file that contains the localized Abstract and Description of a module.
a. Addresses an information gap between INF files and the UEFI Distribution Packaging Specification XML schema
b. There will be an associated update to UPT in BaseTools to consume MODULE_UNI_FILE and associated UNI file during UDP creation that performs the INF -> XML conversion.
c. There will be an associated update to UPT in BaseTools to produce MODULE_UNI_FILE and associated UNI file during UDP installation that performs the XML -> INF conversion.
3. Add Module Extra UNI file that provides the localized Name of a module.
a. [UserExtensions.TianoCore."ExtraFiles"] provides an easy method for a module to specify extra files not listed in [Sources] or [Binaries] sections to be added to a UDP without having to list the files in the UPT package information data file.
b. There will be an associated update to UPT in BaseTools to package up files listed in [UserExtensions.TianoCore."ExtraFiles"] during UDP creation.
c. UNI file contains localized name of a module to go along with the localized Abstract and Description from the MODULE_UNI_FILE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gao, Liming <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15934 6f19259b-4bc3-4df7-8a09-765794883524
1. Usage information in INF file comment blocks are either incomplete or incorrect.
This includes usage information for Protocols/PPIs/GUIDs/PCDs/HOBs/Events/BootModes.
The syntax for usage information in comment blocks is defined in the EDK II Module Information (INF) Specification
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gao, Liming <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15933 6f19259b-4bc3-4df7-8a09-765794883524
2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler.
3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com>
Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524
Its default value is 10 millisecond per IA32 manual.
Platform could customize this PCD value for performance requirement.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15650 6f19259b-4bc3-4df7-8a09-765794883524
GetMemoryCacheTypeFromMtrrType () should return the default memory type instead of UC type for MTRR_CACHE_INVALID_TYPE.
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15053 6f19259b-4bc3-4df7-8a09-765794883524
2. mEnabledInterruptNum is total enabled interrupt number, InterruptType should less than mEnabledInterruptNum.
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15012 6f19259b-4bc3-4df7-8a09-765794883524
Jordan Justen
Jeff Fan
Michael Kinney
Yao, Jiewen
Laszlo Ersek
Hao Wu
Shumin Qiu
Nikolai Saoukh
Anderw Fish
Gao, Liming
Chen Fan
Tian, Hot