Commit Graph

20 Commits

Author SHA1 Message Date
Michael D Kinney 8f7a05e139 IntelSiliconPkg: Replace BSD License with BSD+Patent License
https://bugzilla.tianocore.org/show_bug.cgi?id=1373

Replace BSD 2-Clause License with BSD+Patent License.  This change is
based on the following emails:

  https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html
  https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html

RFCs with detailed process for the license change:

  V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html
  V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html
  V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-04-09 10:58:05 -07:00
Solanki, Digant H 34c5a69a2b IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1454
Based on latest IGD OpRegion Spec, IGD_OPREGION_MBOX3 needs to be updated with two new members : Physical Address of Raw VBT Data (RVDA) and Size of Raw VBT Data (RVDS)

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
2019-01-31 16:24:03 +08:00
Star Zeng c8a2f3c332 IntelSiliconPkg: Move MicrocodeUpdate from UefiCpuPkg
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=540

To consume FIT table for Microcode update,
UefiCpuPkg/Feature/Capsule/MicrocodeUpdateDxe
needs to be updated to consume
IntelSiliconPkg/Include/IndustryStandard/FirmwareInterfaceTable.h,
but UefiCpuPkg could not depend on IntelSiliconPkg.

Since the Microcode update feature is specific to Intel,
we can first move the Microcode update feature code from
UefiCpuPkg to IntelSiliconPkg [first step], then update
the code to consume FIT table [second step].

This patch series is for the first step.

Note: No any code change in this patch, just move.
Next patch will update MicrocodeUpdate to build with the package.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Yonghong Zhu <yonghong.zhu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2017-11-30 09:25:28 +08:00
Jiewen Yao f02c531967 IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.
We notice that there is real usage in PEI to show
the graphic out. As such we need report RMRR table
in PEI to let VTdPmrPei driver skip the IGD UMA region.

Now the VTD_INFO PPI uses the same DMAR data structure.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-20 14:45:42 +08:00
Jiewen Yao 77562d13ac IntelSiliconPkg/include: Add VTD_INFO PPI.
This VTD_INFO_PPI is to provide VTD information in PEI.
As such, we can have a generic VTd driver.

It is a lightweight version DMAR table, but it does
not contain PCI device information.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-16 09:18:03 +08:00
Jiewen Yao 40cc227055 IntelSiliconPkg/Vtd.h: Add definition for PMR.
Add missing PMR definition in VTd spec.

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-09-16 09:17:59 +08:00
Jiewen Yao 71872f7cda IntelSiliconPkg/header: update PlatformVtdPolicy
Add flexible exception list format:
1) Support Device scope based reporting:
Such as, Seg:0/StartBus:0/(Dev:1C|Func:0)/(Dev:0|Func:0)

2) Support PCI VendorId/DeviceId based reporting
Such as, VID:8086|DID:9D2F|Rev:21|SVID:8086|SDID:7270

Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-08-28 16:28:43 +08:00
Star Zeng 76c6f69cca IntelSiliconPkg: Fix VS2015 NOOPT IA32 build failure in IntelVTdDxe
There are VS2015 NOOPT IA32 build failure like below in IntelVTdDxe.
XXX.lib(XXX.obj) : error LNK2001: unresolved external symbol __allshl
XXX.lib(XXX.obj) : error LNK2001: unresolved external symbol __aullshr

This patch is to update Vtd.h to use UINT32 instead of UINT64 for
bitfields in structure definition, and also update IntelVTdDxe code
accordingly.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-08-11 09:30:19 +08:00
Jiewen Yao 4fd8eda9a3 IntelSiliconPkg/Include: Add PlatformVtdPolicy Protocol
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-07-27 09:29:12 +08:00
Jiewen Yao e2d81fb12a IntelSiliconPkg/Include: Add VTD industry standard.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-07-27 09:29:10 +08:00
Dandan Bi 6e9e19aa84 IntelSiliconPkg: Fix format issues
1. Fix doxygen formt
2. Fix Guid format

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-20 10:51:16 +08:00
Giri P Mudusuru d4a9b90fa7 IntelSiliconPkg: Fixed bug in IgdOpregion spec
Spec documents Mailbox3 - RM31 size as 0x45(69) instead of 0x46(70)

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-10-18 03:32:41 -07:00
Giri P Mudusuru ad9448408a IntelSiliconPkg: Add Intel Firmware Version Info (FVI) definitions
Adding Intel Firmware Version Info (FVI) related defines & structures.
FVI enables reporting the Firmware Versions using SMBIOS OEM Type.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-10-13 22:40:49 -07:00
Giri P Mudusuru c3aa61b571 IntelSiliconPkg: Fixing syntax bug in IGD_OPREGION_HEADER
Added missing ; for DVER in IGD_OPREGION_HEADER

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-10-12 03:26:50 -07:00
Giri P Mudusuru 98e059ba16 IntelSiliconPkg: Updated IgdOpregion.h based on latest spec
Updated IgdOpregion.h to align with latest specification
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf

1) Updated Mailbox structures to align with latest spec
2) Added Mailbox 5 structure
3) Added defines for Signature and Mailbox support

Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-10-07 10:09:09 -07:00
Mudusuru, Giri P 72092534a9 IntelSiliconPkg: Rename IGD structures to make it consistent
Renamed INTEL_IGD_* to IGD_* and IGD_OPREGION_VBT to IGD_OPREGION_MBOX4
to make it consistent with file name and other mailbox naming.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-09-03 06:14:18 +08:00
Giri P Mudusuru 648e2a2e7b IntelSiliconPkg: Add Firmware Interface Table (FIT) definitions
Adding Processor Firmware Interface Table (FIT) related defines & structures

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-30 09:30:27 +08:00
Mudusuru, Giri P 5c66efd0ed IntelSiliconPkg: Fixed VBT size bug, typos and updated comments
1) Fixed the VBT size from 0x1C00(7KB) to 0x1800(6KB) and typos, indentation
2) Updated offsets in hex values and offset from start of OPREGION

Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-08-23 11:05:44 +08:00
Jiewen Yao 9fb16e2143 IntelSiliconPkg/IgdOpRegion: Add definition for Intel IGD
OpRegion.

Add IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
Specification.
at https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf

Previous submission seems appears to be cut off. I do not know why.
Add missing part here.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-06-16 08:42:44 +08:00
Jiewen Yao 7e74fd570d IntelSiliconPkg/IgdOpRegion: Add definition for Intel IGD OpRegion.
Add IGD OpRegion definition from Intel Integrated Graphics Device OpRegion
Specification.
at https://01.org/sites/default/files/documentation/acpi_igd_opregion_spec_0.pdf

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-06-15 09:31:30 +08:00