The 'universal' PCI bus driver in MdeModulePkg contains a quirk to
degrade 64-bit PCI MMIO BARs to 32-bit in the presence of an option
ROM on the same PCI controller.
This quirk is highly specific to not just the X64 architecture in general,
but to the PC platform in particular, given that only X64 platforms that
require legacy PC BIOS compatibility require it. However, making the
quirk dependent on the presence of the legacy BIOS protocol met with
resistance, due to the fact that it introduces a dependency on the
IntelFrameworkModulePkg package.
So instead, make the quirk configurable, by introducing a feature flag PCD
'PcdPciDegradeResourceForOptionRom' which defaults to TRUE only for X64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.
As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.
As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely
ignored by the PCI host bridge driver, which means that, on an implementation
that supports DMA above 4 GB, allocations above 4 GB may be provided to
devices that have not expressed support for it.
So in addition to checking 'RootBridge->DmaAbove4G' to establish whether the
root bridge itself supports DMA above 4 GB, we must also take into account
the operation type (EfiPciOperationBusMaster{Read|Write|CommonBuffer}64),
and the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, when mapping and
allocating DMA memory, respectively.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
Since current codes in NvmExpressDxe already support the non-blocking I/O
feature for EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface, the relative bit
in the 'Attributes' field of EFI_NVM_EXPRESS_PASS_THRU_MODE should be set
to reflect this.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit fixes the issue that the caller event passed to
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() will not be signaled for
NVME Admin commands.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
According to the UEFI spec, EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru()
should return EFI_INVALID_PARAMETER if the input 'NamespaceId' is invalid
for the NVM Express controller. This commit adds check in PassThru() to
follow this rule.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit adds serveral checks for the 'Packet' parameter passed to the
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() API:
The check for the 'TransferLength' field in
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET to make sure the value will not
exceed the maximum data transfer size allowed by a controller.
The check for the 'TransferBuffer' and 'TransferLength' fields in
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET when the Opcode of an NVME
command indicates a data transfer between controller and host.
The check for the 'MetadataLength' field in
EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET to make sure the value is not 0
when the corresponding 'MetadataBuffer' field has a non-NULL value.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
According to UEFI spec, an EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL with neither
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor
EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set in the Attributes field
is an illegal configuration.
This commit adds this check in the PassThru API to follow the spec.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
According to the UEFI spec, the 'TransferBuffer' and 'MetadataBuffer' used
in a data transfer should be aligned on the boundary specified by the
IoAlign field in the EFI_NVM_EXPRESS_PASS_THRU_MODE structure.
This commit adds this check to follow the spec.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
According to the UEFI spec,
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() should return
EFI_NOT_FOUND when the value pointed to by NamespaceId is the namespace ID
of the last namespace on the NVM Express controller. This commit modifies
the check for NamespaceId to follow this rule.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
According to the UEFI spec,
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() should return
EFI_NOT_FOUND when the input DevicePath is a device path node type that
the NVM Express Pass Thru driver supports, but there is not a valid
translation from DevicePath to a namespace ID. Current code will return
EFI_SUCCESS. This commit adds additional check in the GetNameSpace API to
make sure correct status is returned.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
According to the UEFI spec,
EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() should return
EFI_NOT_FOUND when the input NamespaceId is not valid. However, current
code returns EFI_DEVICE_ERROR instead. This commit modifies the check for
input NamespaceId to return the correct status.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The gBS->OpenProtocol() calls to open EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL
in NvmExpress.c will crash the data in 'Mode' field of
'Private->Passthru'.
The third parameter of gBS->OpenProtocol() is an output parameter that
stores the address where a pointer to the corresponding Protocol
Interface. The current code mistakenly pass '&Private->Passthru' (a
pointer of the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL) as the third
parameter. This will crash the data in 'Mode' filed.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The retry mechanism will bring issue if the usb device is unplugged
from XHCI HC but s/w is trying to access it through BlockIo. The
current cmd will get device error return status, but the sequential
cmds will be timeout. This behavior will cause system unresponsive
for a long while and bring bad user experience.
So we break the retry loop if found device error.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
The last TRB in transfer ring is a LINK type TRB, which shouldn't
be accounted as a valid item in IsAsyncIntTrb().
Without this fix, the original algo will bring issue on those URBs
whose TRBs crosses the transfer ring.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This change is used to remove the port status polling in port reset
functions.
Why it's needed is because:
1) The same polling on same port has taken place prior to this removed
one. See UsbEnumeratePort()->GetPortStatus(). So this polling in
UsbEnumerateNewDev()->ResetPort() is redundant.
2) EDKII Xhci driver hooks all GetPortStatus() operations. If we don't
remove this one, XHCI driver's XhcPollPortStatusChange() may enter twice
in reset process and wrongly think the device is unplugged.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
The Host Controller reset has been done at EDKII UHCI/EHCI/XHCI, The
original code will do twice host controller initialization which is
unnecessary. It also bring issues on some USB HCs.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
> cc1: warnings being treated as errors
> MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c:
> In function 'GetProposedResources':
> MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c:1388:
> error: integer constant is too large for 'long' type
Append a ULL suffix to the replacement text of PCI_RESOURCE_LESS that is
aligned with the style of the EFI_RESOURCE_SATISFIED and
EFI_RESOURCE_NOT_SATISFIED macros.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Section 7.8.2 of the PCI Express specification (r4.0 v0.3), entitled "PCI
Express Capabilities Register (Offset 02h)", and section 7.8.9 "Slot
Capabilities Register (Offset 14h)" of the same, describe the conditions
when a PCIe port should be considered "supporting hotplug":
- it should be a root complex port or a switch downstream port, and
- it should have the "Slot Implemented" bit set in the Express
Capabilities Register, and
- it should have the "Hot-Plug Capable" bit set in the Slot Capabilities
Register.
The first two sub-conditions are already implemented in at least two open
source projects I could find:
- in SeaBIOS by Marcel Apfelbaum: "hw/pci: reserve IO and mem for pci
express downstream ports with no devices attached"
<https://code.coreboot.org/p/seabios/source/commit/3aa31d7d6375>,
- in edk2 itself, in the implementation of the "PCI" UEFI Shell command:
see the "PcieExplainTypeSlot" case label in function
PciExplainPciExpress(), file
"ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c".
PciBusDxe recognizes such PCIe ports as bridges, but it doesn't realize
they support hotplug. In turn PciBusDxe omits getting any resource padding
information from the platform's EFI_PCI_HOT_PLUG_INIT_PROTOCOL for these
bridges:
GatherPpbInfo() [PciEnumeratorSupport.c]
GetResourcePaddingPpb() [PciResourceSupport.c]
GetResourcePaddingForHpb() [PciHotPlugSupport.c]
IsPciHotPlugBus() [PciHotPlugSupport.c]
//
// returns FALSE
//
//
// the following is not reached:
//
gPciHotPlugInit->GetResourcePadding()
Implement a function called SupportsPcieHotplug() for identifying such
ports, and call it from IsPciHotPlugBus() (after the call to IsSHPC()).
Cc: "Johnson, Brian J." <bjohnson@sgi.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
The PCI Hot Plug capability register block is marked with capability ID
0x0C (EFI_PCI_CAPABILITY_ID_SHPC), not 0x06
(EFI_PCI_CAPABILITY_ID_HOTPLUG).
This bug prevents PciBusDxe from recognizing whether a PCI-to-PCI bridge
supports hotplug. In turn the platform's EFI_PCI_HOT_PLUG_INIT_PROTOCOL is
not consulted for resource padding information:
GatherPpbInfo() [PciEnumeratorSupport.c]
GetResourcePaddingPpb() [PciResourceSupport.c]
GetResourcePaddingForHpb() [PciHotPlugSupport.c]
IsPciHotPlugBus() [PciHotPlugSupport.c]
IsSHPC() [PciHotPlugSupport.c]
//
// returns FALSE
//
//
// the following is not reached:
//
gPciHotPlugInit->GetResourcePadding()
Look for the correct capability ID.
Cc: "Johnson, Brian J." <bjohnson@sgi.com>
Cc: Alex Williamson <alex.williamson@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
If there is no port multiplier (PortMultiplierPort = 0xFFFF), current code
in functions TransferAtaDevice() and TrustTransferAtaDevice() will always
set the DEV bit of the ATA device register. It causes that ATA commands
cannot be sent to some ATA hard drives.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
- abstrated to abstracted
- accessibla to accessible
- addres to address
- apropriate to appropriate
- arry to array
- availabe to available
- avaliable to available
- becasue to because
- correponding to corresponding
- etablished to established
- exeuction to execution
- extensiable to extensible
- fileds to fields
- loadding to loading
- ptototypes to prototypes
- prococol protocol
- requried to required
- resoruce to resource
- runing to running
- uild to build
Cc: Star Zeng <star.zeng@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The commit makes sure that the elements in array 'SwitchResp' get
initialized before being used.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This change is to avoid UEFI SCT failure as UEFI SCT has no knowledge
about how to accessing a EMMC RPMB partition.
The user needs to access RPMB partition should get access through
EFI_SD_MMC_PASS_THRU protocol with authentication key & mac.
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
We have to upgrade the TPL level used by SdMmc stack because the
following flow:
DiskIo2ReadWriteDisk() in logical partition -> PartitionReadBlocksEx()
in logical partition at TPL callback level -> ProbeMediaStatusEx()
with sync request -> DiskIo2ReadWriteDisk() in physical partition ->
waiting for async task completion.
if the low layer driver doesn't run at TPL_NOTIFY level, it will have
no time to trigger async task and cause system hang.
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
According to spec if the length of a descriptor is smaller than
what the specification defines, then the host shall ignore it.
However if the size is greater than expected the host will ignore
the extra bytes and start looking for the next descriptor
at the end of actual length returned. Original check did not
handle the latter case correctly and only allowed descriptors
with lengths exactly as defined in specification.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evgeny Yakovlev <insoreiges@gmail.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This delay is necessary for eMMC reset to working properly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Joe Zhou <shjzhou@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
It is enough to set PxCMD.FRE bit, which cause HBA to post received FISes
into the FIS receive area. According to AHCI Specification, only polling on
PxCMD.FRE to be cleared is necessary, when it is needeed to stop FIS engine
(eg. in order to change PxCMD.FB address).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
It is the follow up of 3ab41b7a32
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
If there is no multiplier, the DEV bit of the ATA device register would
always be set. It causes that some ATA hard drives don't response the
ATA identity command sent to them.
Below is the description about DEV bit in ATA spec:
A device is selected when the DEV bit of the Device register is equal to
the device number assigned to the device by means of a Device 0/Device 1
jumper or switch, or use of the CSEL signal.
Below is the description about DEV bit in SATA spec:
When the DEV bit in the Device register is set to one, selecting the
non-existent Device 1, the host adapter shall respond to register reads
and writes as specified for a Device 0 with no Device 1 present, as
defined in the ATA/ATAPI-5 standard.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Cinnamon Shia <cinnamon.shia@hpe.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
The Maximum Queue Entries Supported (MQES) field in the CAP (Controller
Capabilities) register for a NVMe controller restrict the maximum
individual queue size that the controller supports.
The origin code does not check this value and always uses a hardcode value
when creating I/O submission/completion queues for asynchronous
transmission. The hardcode value might be larger than the MQES field, this
will lead to an 'Invalid Queue Size' error when creating I/O
submission/completion queues.
The patch will add checks to make sure proper queue size is passed when
creating I/O submission/completion queues.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
Move NvmExpressHci.h definitions to a public industry standard
header in MdePkg. The NvmExpressHci.h contains definitions based
on the NVMe v1.1 specification. These definitions should be in
a public header so that clients of the NVMe passthru protocol
can use them to execute NVMe commands.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Darbin Reyes <darbin.emm.reyes@hpe.com>
Reviewed-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hpe.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
The driver entry point calls gDS->SetMemorySpaceAttributes().
This interface may return EFI_NOT_AVAILABLE_YET when CPU Arch
protocol is not available.
So we need to list CpuArch protocol in its INF dependency section.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
PciBus driver originally always degrade (64->32) the MMIO resource
for PCI BAR when the PCI device contains option ROM.
But the degrade causes the PCI device can only use resource below 4GB
which makes the resource allocation fails when the PCI device wants
very big MMIO.
The patch follows the PI spec (ECR 1529) to honor the granularity
setting for PCI BAR from IncompatiblePciDeviceSupport so that even
for PCI device which contains option ROM, the degrade doesn't happen
if IncompatiblePciDeviceSupport returns 64 as granularity.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Remove "Efi" from gEfiIncompatiblePciDeviceSupport to shorten
the global variable name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
This patch implements the EFI_ERASE_BLOCK_PROTOCOL in ScsiDiskDxe driver.
For now, the codes support the erase block feature only on Universal Flash
Storage (UFS) devices.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Ruiyu Ni
Ard Biesheuvel
Feng Tian
Hao Wu
Laszlo Ersek
Giri P Mudusuru
Evgeny Yakovlev
Joe Zhou
Jan D?bro?
Star Zeng
Cinnamon Shia
Darbin Reyes