parse reads data from StdIn when pipe is used and does not require –sfo output stored in a file. (e.g.: fs0:\> ls *.nsh –sfo | parse FileInfo 2)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tapan Shah <tapandshah@hp.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17555 6f19259b-4bc3-4df7-8a09-765794883524
Corrects a word typo and a comment error.
Rename a label to match its function name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Yao Jiewen <Jiewen.Yao@intel.com>
Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17553 6f19259b-4bc3-4df7-8a09-765794883524
Follow IDE BUS Master spec to ensure the PRDT table not cross 64k
boundary in memory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17552 6f19259b-4bc3-4df7-8a09-765794883524
Replace tabs with whitespaces and remove the trailing whitespaces
at the end of lines to conform to the coding style.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17551 6f19259b-4bc3-4df7-8a09-765794883524
The current coreboot UEFI payload has an assumption that all interrupt
sources should be masked off before transferring control to the payload.
However, it is not the case on some platforms, such as QEMU. It will
cause boot failure due to unexpected pending interrupt in the payload.
To resolve it all legacy 8259 interrupt sources need to be masked
piror to the DXE phase. The fix was tested on QEMU virtual platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17550 6f19259b-4bc3-4df7-8a09-765794883524
The EMBED command allows you to put one or more UPD data into a specify data structure.
You can utilize it as a group of UPD for example.
You must specify a start and an end for the specify data structure.
Example:
!HDR EMBED:{MY_DATA_STRUCT:MyDataStructure:START}
gTokenSpaceGuid.Upd1 | 0x0020 | 0x01 | 0x00
gTokenSpaceGuid.Upd2 | 0x0021 | 0x01 | 0x00
!HDR EMBED:{MY_DATA_STRUCT:MyDataStructure:END}
gTokenSpaceGuid.UpdN | 0x0022 | 0x01 | 0x00
Result:
typedef struct {
/** Offset 0x0020
**/
UINT8 Upd1;
/** Offset 0x0021
**/
UINT8 Upd2;
/** Offset 0x0022
**/
UINT8 UpdN;
} MY_DATA_STRUCT;
typedef struct _UPD_DATA_REGION {
…
/** Offset 0x0020
**/
MY_DATA_STRUCT MyDataStruct;
…
} UPD_DATA_REGION;
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17549 6f19259b-4bc3-4df7-8a09-765794883524
For boot performance dump, as current behavior.
It depends on which PerformanceLib instance the DP application linked to.
For example, if DxePerfrmanceLib(MdeModulePkg\Library\DxePerformanceLib)
got linked, it will try to dump PEI and DXE performance data; and if
DxeSmmPerfrmanceLib(MdeModulePkg\Library\DxeSmmPerformanceLib)
got linked, then SMM performance data are expected.
It has burden and confusion to developers about the DP application need to be linked to
different PerformanceLib instance in *.dsc and rebuilt for the performance data dump.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17548 6f19259b-4bc3-4df7-8a09-765794883524
This API can be used for platform to customize the boot description other than using core provided boot description.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17547 6f19259b-4bc3-4df7-8a09-765794883524
For *.asm and *.s, there have been cases of *.Asm and *.S files, but
since the nasm extensions are new, we don't need to support the upper
case extensions.
In other words, remove .Nasm and .NASM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17544 6f19259b-4bc3-4df7-8a09-765794883524
The debug message is to print the current TPL and requested TPL value.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17543 6f19259b-4bc3-4df7-8a09-765794883524
Move ACPI default PCDs
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
from [PcdsFixedAtBuild, PcdsPatchableInModule] to
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
to cover some platforms want to update them at boot time.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17542 6f19259b-4bc3-4df7-8a09-765794883524
Leif becomes a co-maintainer for the ARM Packages.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17541 6f19259b-4bc3-4df7-8a09-765794883524
This new helper function allows to install ACPI Table on condition.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17540 6f19259b-4bc3-4df7-8a09-765794883524
The TFTP Device Path might contain a list of File Path device
path nodes.
ConvertDevicePathToText() allows to concatenate these File Path
nodes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17539 6f19259b-4bc3-4df7-8a09-765794883524
ARM toolchain raises the build error: "enumerated type mixed with
another type".
To fix the issue, typecase can be used like below.
- return EfiMaxMemoryType + 1;
+ return (EFI_MEMORY_TYPE)(EfiMaxMemoryType + 1);
But to eliminate the confusion, update the return type of
GetProfileMemoryIndex() from EFI_MEMORY_TYPE to UINTN.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17535 6f19259b-4bc3-4df7-8a09-765794883524
This updates help output to put dynamic commands in correct alphabetical location mixed into the other commands.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Tapan Shah <tapandshah@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17534 6f19259b-4bc3-4df7-8a09-765794883524
Add string ” DTS” and help info string” Enabled/Disable Digital Thermal Sensor”.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17531 6f19259b-4bc3-4df7-8a09-765794883524
ARM toolchain raises the error: "statement is unreachable"
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17529 6f19259b-4bc3-4df7-8a09-765794883524
The PCI Root bridge is defined by PciRoot(0x0)/Pci(0x0,0x0).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Ronald Cron <Ronald.Cron@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17528 6f19259b-4bc3-4df7-8a09-765794883524
1. Data type for GcdMemoryType and GcdIoType is enumeration type
rather than bit field, so we need to use strict equation "=="
instead of bit-and "&";
2. Testing for GcdIoType should use EfiGcdIoType*** constants
rather than EfiGcdMemoryType***;
3. As we are going to use strict equation, it is clearer to use
switch-case than if-else.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17527 6f19259b-4bc3-4df7-8a09-765794883524
The VA address space has a maximum address width of 48 bits in
AArch64 state; 48 bits address width limit will provide better
compatibility than 40 bits for future CPU.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17526 6f19259b-4bc3-4df7-8a09-765794883524
LocatePciExpressCapabilityRegBlock () doesn't check the return status of Pci.Read().
Certain platform's PciRootBridge.Pci.Read() doesn't support PCIE access causing the CapabilityEntry not updated.
If the uninitialized CapabilityEntry equals to a big enough initial value, the while-loop will never end.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17513 6f19259b-4bc3-4df7-8a09-765794883524
fix bellow bug:
change checkbox from FALSE to TRUE.EFI_BROWSER_ACTION_CHANGED called
but when checkbox change back to FALSE,don't call EFI_BROWSER_ACTION_CHANGED
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17512 6f19259b-4bc3-4df7-8a09-765794883524
*_*_*_*_BUILDRULEORDER = nasm Nasm NASM asm Asm ASM S s
*_XCODE32_*_*_BUILDRULEORDER = S s nasm Nasm NASM
*_XCLANG_*_*_BUILDRULEORDER = S s nasm Nasm NASM
*_XCODE5_*_*_BUILDRULEORDER = S s nasm Nasm NASM
Tool Chain in Mac Os will use S as the first priority. Other tool chains
use nasm as the first priority.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yingke Liu <yingke.d.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17510 6f19259b-4bc3-4df7-8a09-765794883524
This feature allows the toolchain to choose a preference for source file
extensions in tools_def.txt. The first extension is given the highest priority.
Here is an example usage for tools_def.txt:
*_*_*_*_BUILDRULEORDER = nasm Nasm NASM asm Asm ASM S s
*_XCODE5_*_*_BUILDRULEORDER = S s nasm Nasm NASM
Now, if a .inf lists these sources: 1.nasm, 1.asm and 1.S
All toolchains, except XCODE5 will use the 1.nasm file. The XCODE5
toolchain will use the 1.S file.
Note that the build_rule.txt file also impacts the decision, because,
for instance there is no build rule for .asm files on GCC toolchains.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yingke Liu <yingke.d.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17509 6f19259b-4bc3-4df7-8a09-765794883524
The patch also fixed some comments to align the code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17507 6f19259b-4bc3-4df7-8a09-765794883524
A previous incorrect check-in adds the IsaBusDxe driver to <Root>/Bus directory.
The patch fixes it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17506 6f19259b-4bc3-4df7-8a09-765794883524
A previous incorrect check-in adds the SIO header files to <Root>/Include directory.
The patch fixes it.
The patch also adds the missing PeiServices pointer to the SIO PPI interfaces.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17505 6f19259b-4bc3-4df7-8a09-765794883524
This driver follows UEFI driver model and layers on ISA HC protocol defined in PI spec 1.2.1.
It consumes the ISA Host Controller protocol produced by the ISA Host Controller and installs the ISA Host Controller Service Binding protocol on the ISA Host Controller's handle.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17504 6f19259b-4bc3-4df7-8a09-765794883524
Tapan Shah
Ard Biesheuvel
Guo Dong
Feng Tian
Maurice Ma
Star Zeng
Ruiyu Ni
David Wei
Jordan Justen
Olivier Martin
Jaben Carsey
Shifei Lu
Heyi Guo
Hao Wu
Eric Dong
Dandan Bi
Yingke Liu