The storage space for virtio-scsi request header being shared
with the host was from the stack as the request structure was
a local function variable.
A bug in the VMM can corrupt the stack space, and such issues
can be very hard to debug.
Note: This is only an issue with a normal guest VM (non-CCA).
A CCA guest VM would perform bounce buffering for sharing the
data and therefore not have this issue.
Instead of using the stack for sharing the data with the host,
memory can be allocated from the heap pool. However, pool
allocations are not any safer in terms of pages being shared
between different allocations, and so mapping a pool allocation
for DMA may expose it to potential corruption by the VMM in
exactly the same way. The only difference is the potential
impact on program behaviour, which is much higher with the
stack.
Additionally, for guest-side corruption heap allocations can
take advantage by turning on heap guard to help find the bug.
Therefore, minor improvement can be achieved by allocating
memory for the virtio-scsi request header from the heap for
sharing with the host.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
The storage space for virtio-blk request header being shared
with the host was from the stack as the request structure was
a local function variable.
A bug in the VMM can corrupt the stack space, and such issues
can be very hard to debug.
Note: This is only an issue with a normal guest VM (non-CCA).
A CCA guest VM would perform bounce buffering for sharing the
data and therefore not have this issue.
Instead of using the stack for sharing the data with the host,
memory can be allocated from the heap pool. However, pool
allocations are not any safer in terms of pages being shared
between different allocations, and so mapping a pool allocation
for DMA may expose it to potential corruption by the VMM in
exactly the same way. The only difference is the potential
impact on program behaviour, which is much higher with the
stack.
Additionally, for guest-side corruption heap allocations can
take advantage by turning on heap guard to help find the bug.
Therefore, minor improvement can be achieved by allocating
memory for the virtio-blk request header from the heap for
sharing with the host.
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Retire the ancient reset runtime DXE in EmbeddedPkg, and the associated
EfiResetSystemLib library class and template implementation. These are
incomplete and have been superseded by a generic implementation in
MdeModulePkg.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
These libraries do not implement EfiResetSystemLib to begin with, and
this library class is going to be dropped. So drop these bogus
references first.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Add Report status code events to Nvme to trigger when timeouts occur.
This improves traceability when critical errors happen.
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
- Remove the hardcoded definition (UFS_INIT_COMPLETION_TIMEOUT)
- Migrate the UFS initial completion timeout into PCD value
Signed-off-by: Jason1 Lin <jason1.lin@intel.com>
- Remove the hardcoded definition (UFS_INIT_COMPLETION_TIMEOUT)
- Migrate the UFS initial completion timeout into PCD value
Signed-off-by: Jason1 Lin <jason1.lin@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4820
- Add the PCD to indicate the UFS device initialize completion time
- Default value of this PCD value is 600ms
Signed-off-by: Jason1 Lin <jason1.lin@intel.com>
REF : https://bugzilla.tianocore.org/show_bug.cgi?id=4750
Migrate the FV that doesn't contain the currently executing PEI Core
when permanent memory is initialized but PEI Core is still potentially
running from faster memory (Tepmorary RAM). This may reduce the time
required to migrate FVs to permanent memory. The FV containing PEI
Core is migrated after the PEI Core reentry when it is executed from
permanent memory.
This may or may not improve performance depending on the behavior of
temporary RAM and the actual performance changes must be measured with
the feature enabled and disabled.
This migration algorithm is only used for FVs specified in the
gEdkiiMigrationInfoGuid HOB and built with flag
FLAGS_FV_MIGRATE_BEFORE_PEI_CORE_REENTRY.
Signed-off-by: Awiral Shrivastava <awiral.shrivastava@intel.com>
Start the build with TOOL_CHAIN_TAG VS2015 by launch:
Build -t VS2015
ERROR: Would get following build error message:
'c:\Program' is not recognized as an internal or external command,
operable program or batch file.
NMAKE : fatal error U1077: '"c:\Program Files\Windows Kits\8.1\bin\x86\\rc.exe' : return code '0x1'
Stop.
Fix the build error,
Tested :
TOOL_CHAIN_TAG = VS2015 (>Build -t VS2015)
TOOL_CHAIN_TAG = VS2015x86 (>Build -t VS2015x86)
Signed-off-by: wilson_chen <wilson_chen@phoenix.com>
This modification come from ACPI 6.5 spec.
Besides, Starting with revision 2 of HEST, the Error Source Structures
must be sorted in Type ascending order for Error Source Structure
Types of less than 12.
Signed-off-by: Herman Li <herman.li@intel.com>
Commit 8984fba2f2 added setting the
EFI_MEMORY_XP attribute on DMA buffers. However, it did not ensure
that the XP capability was set on that region.
This patch adds setting the XP capability before attempting to set
the attribute. If setting the capability fails, it defaults to the
old behavior of not setting the XP bit.
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
For X64 builds, the EFIAPI is replaced by '(__attribute__((ms_abi))'.
This might lead to build error for some ACPI tablte generators
due to function prototype mismatch.
Add the EFIAPI to ACPI table generator hooks:
- ACPI_TABLE_GENERATOR_BUILD_TABLEEX
- ACPI_TABLE_GENERATOR_FREE_TABLEEX
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Some CM objects fields are wider than the targeted field in ACPI
tables. Some assignments are also subject to data loss and
trigger the following warnings:
- '<': signed/unsigned mismatch
- '=': conversion from 'UINTxx' to 'UINTyy', possible loss of data
with xx > yy.
Add checks/cast to remove the warnings.
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Parent interrupt controller's address cells is arch specific. So,
create a wrapper function which can be implemented differently for
different archs. Move current implementation to ARM specific file.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
The interrupts property in DT is arch specific.
Move the current implementation and the way to decode the property
to the Arm folder to prepare for other architecture support.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
ArmLib.h is required only for building GIC in ARM. So, move it to ARM
specific file. Otherwise, FdtHwInfoParserInclude.h being a common header
across architectures will have issue on other architectures.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
To allow other architectures to potentially re-use the serial port
parser and make the code arch neutral, remove the Arm prefixes.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
To allow other architectures to potentially re-use the serial port
parser and make the code arch neutral, remove the Arm prefixes.
Also remove the check searching for a GIC version.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
To allow other architectures to potentially re-use the serial port
parser and make the code arch neutral, make the MainDispatcher()
function arch specific.
Other architectures can choose which parse/dispatcher are desired
to be called through the configuration of the HwInfoParserTable.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Create an Arm directory in the FdtHwInfoParserLib as a preparation
step to support other architectures.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Mandatory ACPI tables depend on the architectures.
Different architectures might also want to check other tables.
Move mAcpiVerifyTables containing the list of ACPI tables to check
to an arch specific file and introduce GetAcpiTablePresenceInfo()
to get get the relevant information from the array.
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
The GICC is an ARM specific structure. Other architectures have different
local interrupt controller structures from which CPU topology can be
created. Avoid the GICC reference in common code by:
- creating a wrapper CreateTopologyFromIntC() instead of
CreateTopologyFromGicC() so that different archs can implement
it differently.
- implementing arch specific functions to get the AcpiProcessorUid,
CpcToken, EtToken and use them instead of using the GicC CM object
directly.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Allow other architectures to reuse the AcpiSratLib by extracting
the Arm specific part of the table generation.
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Remove the Arm name from the generator to show the generator
can be used by other archs.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Allow other architectures to reuse the AcpiDbg2Lib by extracting
the Arm specific part of the table generation.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Allow other architectures to reuse the AcpiFadtLib by extracting
the Arm specific part of the table generation.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Allow other architectures to reuse ACPI common libraries by:
- Removing the Arm prefix from the BASE_NAME
- Moving Arm specific libraries/packages to ARM/AARCH64
specific sections in the .inf files
Also remove the empty .inf sections.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Some of the ACPI table generators are generic enough to be re-used
by other architectures. Move the following generators to a
'Common' folder:
- AcpiDbg2Lib
- AcpiFadtLib
- AcpiMcfgLib
- AcpiPcctLib
- AcpiPpttLib
- AcpiRawLib
- AcpiSpcrLib
- AcpiSratLib
- SsdtSerialPortLib
- SsdtCpuTopologyLib
- SsdtPcieLib
and update DynamicTables.dsc.inc accordingly.
Suggested-by: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
Move the PSD info object from Arm Namespace to the Arch Common
namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SSDT CPU topology generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the PCC Subspace Type 5 info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PCCT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the PCC Subspace Type 3 & 4 info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PCCT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the PCC Subspace Type2 info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PCCT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the PCC Subspace Type1 info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PCCT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the PCC Subspace Type0 info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PCCT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the Continuous perfformance control info object from Arm
Namespace to the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SSDT CPU topology generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the Cache info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PPTT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the Processor hierarchy info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- PPTT generator
- SSDT CPU topology generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
The GicCToken field in the CM_ARM_PROC_HIERARCHY_INFO structure is
a reference to the associated object which has the corresponding
ACPI Processor ID, e.g. for Arm systems this is a reference to the
CM_ARM_GICC_INFO object.
For other architecture this may be a reference to a similar object
that has the ACPI Processor ID.
Therefore, rename the GicCToken field to a more generic name like
AcpiIdObjectToken.
Correspondingly also update the following modules to reflect the
changes introduced by this renaming:
- PPTT generator
- SSDT CPu topology generator
- ConfigurationManagerObjectParser.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the LPI info object from Arm Namespace to the
Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SSDT Cpu Topology generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the Generic Initiator affinity info object from Arm Namespace to
the Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SRAT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the PCI device Handle object from Arm Namespace to the
Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SRAT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the ACPI device Handle object from Arm Namespace to the
Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SRAT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move the Memory Affinity Info object from Arm Namespace to the
Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SRAT generator
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Move Pci Interrupt Map Info object from Arm Namespace to the
Arch Common namespace.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SSDT PCIe library
- ConfigurationManagerObjectParser
- Dynamic Plat Repo TokenFixer map
- FdtHwInfoParserLib/Pci/ArmPciConfigSpaceParser.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
The CM_ARM_GENERIC_INTERRUPT struct describes a standard interrupt and
is generic. Therefore move it to the Arch Common namespace header file
and rename it as CM_ARCH_COMMON_GENERIC_INTERRUPT.
Correspondingly also update the following modules to reflect the
changes introduced by the move:
- SSDT CMN600 generator
- ConfigurationManagerObjectParser
- FdtHwInfoParserLib/Pci/ArmPciConfigSpaceParser.
Cc: Pierre Gondois <Pierre.Gondois@arm.com>
Cc: Yeo Reum Yun <YeoReum.Yun@arm.com>
Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com>
Cc: Jeshua Smith <jeshuas@nvidia.com>
Cc: Jeff Brasen <jbrasen@nvidia.com>
Cc: Girish Mahadevan <gmahadevan@nvidia.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Sami Mujawar
Ard Biesheuvel
Leif Lindholm
Sean Brogan
Jason1 Lin
Awiral Shrivastava
wilson_chen
Abhishek Mainkar
Herman Li
Oliver Smith-Denny
Pierre Gondois