Commit Graph

500 Commits

Author SHA1 Message Date
Ard Biesheuvel 521f3cedac ArmPkg: move ARM version of SetMemoryAttributes to ArmMmuLib
... where it belongs, since AARCH64 already keeps it there, and
non DXE users of ArmMmuLib (such as DxeIpl, for the non-executable
stack) may need its functionality as well.

While at it, rename SetMemoryAttributes to ArmSetMemoryAttributes,
and make any functions that are not exported STATIC. Also, replace
an explicit gBS->AllocatePages() call [which is DXE specific] with
MemoryAllocationLib::AllocatePages().

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-03-07 09:38:08 +01:00
Ard Biesheuvel f49ea03de7 ArmPkg/ArmMmuLib: use correct return type for exported functions
The routines ArmConfigureMmu(), SetMemoryAttributes() [*] and the
various set/clear read-only/no-exec routines are declared as returning
EFI_STATUS in the respective header files, so align the definitions with
that.

* SetMemoryAttributes() is declared in the wrong header (and defined in
  ArmMmuLib for AARCH64 and in CpuDxe for ARM)

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-03-07 09:37:09 +01:00
Ard Biesheuvel a76d0e88c3 ArmPkg: remove DebugUncachedMemoryAllocationLib
The debug implementation of the UncachedMemoryAllocationLib library
class relies on the creation of an uncached alias of a memory range,
while keeping the original cached mapping, but with read-only attributes
to trap inadvertent write accesses.

This is not a terribly good idea, given that the ARM architecture does
not allow mismatched attributes, and so creating them deliberately is
not something we should encourage by doing it in reference code.

So remove the library, and replace all references to it with a reference
to the non-debug version (unless the platform does not require a resolution
for it in the first place, in which case all UncachedMemoryAllocationLib
references can be removed altogether).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-23 17:56:10 +00:00
Ard Biesheuvel 526f160f31 ArmPkg/ArmMmuLib: AARCH64: enable stack alignment checking
Enable the hardware stack alignment check, as mandated by the UEFI spec.
This ensures that the stack pointer is 16 byte aligned at each instance
where it is used as the base address in a load/store operation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-22 13:22:42 +00:00
Ard Biesheuvel 97f0d01d5d ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managed
In preparation of enabling stack alignment checking, which is mandated
by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-22 13:22:42 +00:00
Ard Biesheuvel de2a78247a ArmPkg/ArmLib: AARCH64: set frame pointer in cache maintenance routine
Stack and unstack the frame pointer according to the AAPCS in
AArch64AllDataCachesOperation ().

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-22 13:22:41 +00:00
Ard Biesheuvel e0307a7dad ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions
Since the new DXE page protection for PE/COFF images may invoke
EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission
attributes set, add support for this in the AARCH64 MMU code.

Move the EFI_MEMORY_CACHETYPE_MASK macro to a shared location between
CpuDxe and ArmMmuLib so we don't have to introduce yet another
definition.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-02-21 17:23:03 +00:00
Jiewen Yao b7a09b71b6 ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage
Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection,
according to UEFI spec, we should use EFI_MEMORY_RO for write protection.
The EFI_MEMORY_WP is the cache attribute instead of memory attribute.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2017-02-21 17:23:03 +00:00
Ard Biesheuvel aa961dea1e ArmPkg/ArmMmuLib: Revert "use a pool allocation for the root table"
This reverts commit d32702d2c2.

Using a pool allocation for the root translation table seemed like
a good idea at the time, but as it turns out, such allocations are
handled in a way that makes them unsuitable for this purpose: they
are backed by HOBs that don't remain in the same place during the
various PI phase changes, which means the address programmed into
the TTBR register is no longer valid, and may refer to memory that
is reported as available to the OS.

So switch back to using a page based allocation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-01-20 17:50:40 +00:00
Ard Biesheuvel 734bd6cc41 ArmPkg/ArmLib: remove indirection layer from timer register accessors
The generic timer support libraries call the actual system register
accessor function via a single pair of functions ArmArchTimerReadReg()
and ArmArchTimerWriteReg(), which take an enum argument to identify
the register, and return output values by pointer reference.

Since these functions are never called with a non-immediate argument,
we can simply replace each invocation with the underlying system register
accessor instead. This is mostly functionally equivalent, with the
exception of the bounds check for the enum (which is pointless given the
fact that we never pass a variable), the check for the presence of the
architected timer (which only makes sense for ARMv7, but is highly unlikely
to vary between platforms that are similar enough to run the same firmware
image), and a check for enum values that refer to the HYP view of the timer,
which we never referred to anywhere in the code in the first place.

So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib
and ArmGenericTimerVirtCounterLib implementations to call the system
register accessors directly.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
2017-01-20 15:51:34 +00:00
Leif Lindholm 018c3c0b3e ArmPkg: fix compilation error in ArmDmaLib
Commit 0a99a65d2c ("fix incorrect device address of double buffer")
retained an explicit cast on the variable "Buffer" which became
incorrect with the other changes, leading to compilation failures
with some toolchains. Drop the cast.

Contributed-under: TianoCore Contribution Agreement 1.0
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-12-01 17:02:13 +00:00
Ard Biesheuvel bfe34275a9 ArmPkg/ArmDmaLib: add support for fixed host-to-device DMA offset
Some devices, such as the Raspberry Pi3, have a fixed offset between memory
addresses as seen by the host and as seen by the other bus masters. So add
a new PCD that allows this fixed offset to be recorded, and to be used when
returning device addresses from the DmaLib mapping routines.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-11-30 16:43:14 +00:00
Ard Biesheuvel df8c2668d7 ArmPkg/ArmDmaLib: clean up abuse of device address
In preparation of adding support to ArmDmalib for DMA bus masters whose
view of memory is offset by a constant compared to the CPU's view, clean
up some abuse of the device address.

The device address is not defined in terms of the CPU's address space,
and so it should not be used in CopyMem () or cache maintenance operations
that require a valid mapping. This not only applies to the above use case,
but also to the DebugUncachedMemoryAllocationLib that unmaps the
primary, cached mapping of an allocation, and returns a host address
which is an uncached alias offset by a constant.

Since we should never access the device address from the CPU, there is
no need to record it in the MAPINFO struct. Instead, record the buffer
address in case of double buffering, since we do need to copy the contents
(in case of a bus master write) and free the buffer (in all cases) when
DmaUnmap() is called.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-11-30 16:43:08 +00:00
Ard Biesheuvel 0a99a65d2c ArmPkg/ArmDmaLib: fix incorrect device address of double buffer
If double buffering is not required in DmaMap(), the returned device
address is passed through ConvertToPhysicalAddress () to convert the
host address (which in case of DebugUncachedMemoryAllocationLib is not
1:1 mapped) to a physical address, which is what a device would expect
to be able to perform DMA.

By the same reasoning, a double buffer allocated using DmaAllocateBuffer ()
should be converted in the same way, considering that the buffer is allocated
using UncachedAllocatePages (), to which the above equally applies.

So add the missing ConvertToPhysicalAddress () invocation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-11-30 16:42:59 +00:00
Ard Biesheuvel de2ec785e2 ArmPkg/ArmDmaLib: use DMA buffer alignment from CPU arch protocol
Instead of depending on ArmLib to retrieve the CWG directly, use
the DMA buffer alignment exposed by the CPU arch protocol. This
removes our dependency on ArmLib, which makes the library a bit
more architecture independent.

While we're in there, rename gCpu to mCpu to better reflect its
local scope, and reflow some lines that we're modifying anyway.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-11-30 16:41:55 +00:00
Ard Biesheuvel 35718840ef ArmPkg/ArmMmuLib: support page tables in cacheable memory only
Translation table walks are always cache coherent on ARMv8-A, so cache
maintenance on page tables is never needed. Since there is a risk of
loss of coherency when using mismatched attributes, and given that memory
is mapped cacheable except for extraordinary cases (such as non-coherent
DMA), restrict the page table walker to performing cacheable accesses to
the translation tables.

For DEBUG builds, retain some of the logic so that we can double check
that the memory holding the root translation table is indeed located in
memory that is mapped cacheable.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-11-30 16:12:20 +00:00
Daniil Egranov 84083b12f2 ArmPkg/Library/ArmDmaLib: Deallocate Map buffer in case of error
The patch is fixing memory leak in case of errors.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Tested-by; Ryan Harkin <ryan.harkin@linaro.org>

Style fixes: use goto for error handling, whitespace fixes

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-11-15 13:24:40 +00:00
Ard Biesheuvel 581b4ab93f ArmPkg/BdsLib: eliminate calls to deprecated string functions
Remove calls to deprecated string functions like AsciiStrCpy() and
UnicodeStrToAsciiStr()

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-10-28 12:04:07 +01:00
Ard Biesheuvel 6ed6ecee19 ArmPkg/ArmDmaLib: add missing DxeServicesTableLib dependency
This missing dependency has gone unnoticed until now, but it is breaking
the Omap35xxPkg.dsc build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-10-26 08:54:45 +01:00
Laszlo Ersek a1848bc088 ArmPkg/DefaultExceptionHandlerLib: replace AsciiStrCat() with AsciiStrCatS()
AsciiStrCat() is deprecated / disabled under the
DISABLE_NEW_DEPRECATED_INTERFACES feature test macro.

The caller of CpsrString() is required to pass in "ReturnStr" with 32
CHAR8 elements. (DefaultExceptionHandler() complies with this.) "Str" is
used to build "ReturnStr" gradually. Just before calling AsciiStrCat(),
"Str" points to the then-terminating NUL character in "ReturnStr".

The difference (Str - ReturnStr) gives the number of non-NUL characters
we've written thus far, hence (32 - (Str - ReturnStr)) yields the number
of remaining bytes in ReturnStr, including the ultimately terminating NUL
character.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael Zimmermann <sigmaepsilon92@gmail.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=164
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=165
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-10-25 10:46:42 +02:00
Laszlo Ersek f00ace96f3 ArmPkg/ArmDisassemblerLib: replace AsciiStrCat() with AsciiStrCatS()
AsciiStrCat() is deprecated / disabled under the
DISABLE_NEW_DEPRECATED_INTERFACES feature test macro.

The "Str" variable serves no particular purpose in the MRegList() and
ThumbMRegList() functions; replace it with the pointed-to "mMregListStr" /
"mThumbMregListStr" global variable (as appropriate), so that the new
AsciiStrCatS() calls are as clear as possible.

Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael Zimmermann <sigmaepsilon92@gmail.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=164
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=165
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-10-25 10:46:40 +02:00
Ard Biesheuvel 3be743974a ArmPkg: remove BaseMemoryLibStm
All users have moved to the generic or accelerated versions in MdePkg,
so remove the obsolete BaseMemoryLibStm.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-10-24 16:00:15 +01:00
Gary Lin d0d8a17d4a ArmPkg: Fix typos in comments
- differnt -> different
- Libary -> Library
- intialized -> initialized

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-10-19 16:31:22 +01:00
Ard Biesheuvel 062f9fd2cf ArmPkg/DefaultExceptionHandlerLib: improve formatting of backtrace
Implement the backtrace formattting suggested by Andrew, i.e.,

  IRQ Exception at 0x000000005BE182B0
  PC 0x00005BE182B0 (0x00005BE14000+0x000042B0) [ 0] ArmCpuDxe.dll
  PC 0x00005BE15770 (0x00005BE14000+0x00001770) [ 0] ArmCpuDxe.dll
  PC 0x00005EF08CC8 (0x00005EEEB000+0x0001DCC8) [ 1] DxeCore.dll
  PC 0x00005EF09008 (0x00005EEEB000+0x0001E008) [ 1] DxeCore.dll
  PC 0x00005EEF6ACC (0x00005EEEB000+0x0000BACC) [ 1] DxeCore.dll
  PC 0x00005EF0963C (0x00005EEEB000+0x0001E63C) [ 1] DxeCore.dll
  PC 0x00005EF09A38 (0x00005EEEB000+0x0001EA38) [ 1] DxeCore.dll
  PC 0x00005EF01560 (0x00005EEEB000+0x00016560) [ 1] DxeCore.dll
  PC 0x00005EF02FB4 (0x00005EEEB000+0x00017FB4) [ 1] DxeCore.dll
  PC 0x00005EF03098 (0x00005EEEB000+0x00018098) [ 1] DxeCore.dll
  PC 0x00005EF0460C (0x00005EEEB000+0x0001960C) [ 1] DxeCore.dll
  PC 0x00005EF005C4 (0x00005EEEB000+0x000155C4) [ 1] DxeCore.dll
  PC 0x00005EF00360 (0x00005EEEB000+0x00015360) [ 1] DxeCore.dll
  PC 0x00005EF003C8 (0x00005EEEB000+0x000153C8) [ 1] DxeCore.dll
  PC 0x00005EF128D0 (0x00005EEEB000+0x000278D0) [ 1] DxeCore.dll
  PC 0x00005EF12930 (0x00005EEEB000+0x00027930) [ 1] DxeCore.dll
  PC 0x00005EEEF594 (0x00005EEEB000+0x00004594) [ 1] DxeCore.dll
  PC 0x00005EF0CF18 (0x00005EEEB000+0x00021F18) [ 1] DxeCore.dll
  PC 0x00005EF1A310 (0x00005EEEB000+0x0002F310) [ 1] DxeCore.dll
  PC 0x00005EEF1808 (0x00005EEEB000+0x00006808) [ 1] DxeCore.dll
  PC 0x00005EEF1E48 (0x00005EEEB000+0x00006E48) [ 1] DxeCore.dll
  PC 0x00005EF0A838 (0x00005EEEB000+0x0001F838) [ 1] DxeCore.dll
  PC 0x00005EEED70C (0x00005EEEB000+0x0000270C) [ 1] DxeCore.dll
  PC 0x00005EEEC93C (0x00005EEEB000+0x0000193C) [ 1] DxeCore.dll
  PC 0x00005EEEC024 (0x00005EEEB000+0x00001024) [ 1] DxeCore.dll

  [ 0] /home/ard/build/edk2/Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/AARCH64/ArmPkg/Drivers/CpuDxe/CpuDxe/DEBUG/ArmCpuDxe.dll
  [ 1] /home/ard/build/edk2/Build/ArmVirtQemu-AARCH64/DEBUG_GCC5/AARCH64/MdeModulePkg/Core/Dxe/DxeMain/DEBUG/DxeCore.dll

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-14 14:48:10 +01:00
Ard Biesheuvel dd82465a9f ArmPkg/ArmMmuLib: base page table VA size on GCD memory map size
As reported by Eugene, the practice of sizing the address space in the
virtual memory system based on the maximum address in the table passed
to ArmConfigureMmu() is problematic, since it fails to take into account
the fact that the GCD memory space may be extended at a later time, both
for memory and for MMIO. So instead, choose the VA size identical to the
GCD memory map size, which is based on PcdPrePiCpuMemorySize on ARM
systems.

Reported-by: Eugene Cohen <eugene@hp.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13 13:43:34 +01:00
Ard Biesheuvel d32702d2c2 ArmPkg/ArmMmuLib: use a pool allocation for the root table
Currently, we allocate a full page for the root translation table, even
if the configured translation only requires two entries (16 bytes) for
the root level, which happens to be the case for a 40 bit VA. Likewise,
for a 36-bit VA space, the root table only needs 16 entries of 8 bytes
each, adding up to 128 bytes.

So switch to a pool allocation for the root table if we can, but take into
account that the architecture requires it to be naturally aligned to its
size, i.e., a 64 byte table requires 64 byte alignment, whereas pool
allocations in general are only guaranteed to be aligned to 8 bytes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13 13:43:11 +01:00
Ard Biesheuvel 674e127ef6 ArmPkg/ArmMmuLib: remove bogus alignment of page allocations
In commit 7d189f99d8 ("ArmPkg/Mmu: Fix bug of aligning new allocated
page table"), we fixed a flaw in the logic regarding alignment of newly
allocated translation table pages. However, we all failed to spot that
aligning page based allocations to page size is rather pointless to
begin with, so simply allocate a single page each time we add new pages
to the translation tables.

Also, drop the unnecessary cast.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13 13:43:08 +01:00
Ard Biesheuvel e93cb72e59 ArmPkg/ArmMmuLib: deobfuscate GetRootTranslationTableInfo ()
The relations between T0SZ, the number of translation levels and the
size/alignment of the root table can be expressed in simple arithmetic
expressions, so get rid of the lookup table.

Note that this disregards the fact that the maximum value of T0SZ is
39 not 42 (as one would expect for the smallest VA size using 2 levels)
but since this corresponds to a VA size of 32 MB and 4 MB, respectively,
neither of which are sufficient to run UEFI, we can safely ignore the
distinction.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-13 13:42:57 +01:00
Ard Biesheuvel 1f8f4e33a1 ArmPkg/DefaultExceptionHandlerLib: trim module name in backtrace output
As reported by Vishal, the new backtrace output would be more useful if
it did not contain the full absolute path of each module in the list.
So strip off everything up to the last forward slash or backslash in the
string.

Example output:

  IRQ Exception at 0x000000005EF110E0
  DxeCore.dll loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EF121F0) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EF1289C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFB6B4) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFAA44) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFB450) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF938C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF8D04) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEFA8E8) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF3C14) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEF3E48) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EF0C838) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEEF70C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEEE93C) loaded at 0x000000005EEED000
  called from DxeCore.dll (0x000000005EEEE024) loaded at 0x000000005EEED000

Suggested-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-09 14:03:15 +01:00
Ard Biesheuvel e51a677dea ArmPkg/ArmBaseLib: clean up directory structure
For historical reasons, the files under ArmLib are split up into 'common'
files under Common/, containing common C files as well as AArch64 and Arm
specific asm files, and ArmV7 and AArch64 files under ArmV7/ and AArch64/,
respectively. This presumably dates back to the time when ArmLib supported
different revisions of the 32-bit architecture (i.e., pre-V7)

Since the PI spec requires V7 or later, we can simplify this to Arm/ and
AArch64, which aligns ArmLib with the majority of other modules that carry
ARM or AArch64 specific code.

So move the files around so that shared files live at the same level as
ArmBaseLib.inf, and ARM/AArch64 specific files live in Arm/ or AArch64/,
respectively.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08 16:49:15 +01:00
Ard Biesheuvel 20d988be99 ArmPkg/ArmBaseLib: remove MemoryAllocationLib.h includes
The ArmBaseLib timer code does not depend on MemoryAllocationLib at
all, so remove the #includes referring to it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08 16:49:12 +01:00
Ard Biesheuvel 2bdf3f2ca7 ArmPkg/ArmLib: remove all ArmLib flavors except ArmBaseLib
This removes the following ArmLib implementation, which were, apart from
the fact that they targeted either ARM or AARCH64, fully identical:

  ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
  ArmPkg/Library/ArmLib/AArch64/AArch64LibPei.inf
  ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
  ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
  ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
  ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
  ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf

Only ArmBaseLib remains, which can fulfil the dependencies upon each of
the listed flavors.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08 10:02:45 +01:00
Ard Biesheuvel c52c592a03 ArmPkg/ArmLib: introduce ArmBaseLib
Introduce a new ArmLib version ArmBaseLib, which encapsulates the ARM
version ArmV7Lib and the AArch64 version AArch64Lib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08 09:20:33 +01:00
Ard Biesheuvel 2ede1ac0cc ArmPkg/ArmLib: remove NullArmLib
Remove the NULL instance of ArmLib: it is not currently used, and its
usefulness its dubious.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08 09:20:11 +01:00
Ard Biesheuvel 960d0de80b ArmPkg/DefaultExceptionHandlerLib AARCH64: add minimal backtrace to crash dump
When dumping the CPU state after an unhandled fault, walk the stack
frames and decode the return addresses so we can show a minimal
backtrace. Unfortunately, we do not have sufficient information to
show the function names, but at least we can see the modules and the
return addresses inside the modules.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-07 17:22:39 +01:00
Ard Biesheuvel ec68dc2855 ArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attribute
Clang does not like separate definitions for the __alias__ and the
__weak__ attributes, so merge the definitions into one.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-06 15:49:40 +01:00
Ard Biesheuvel bc54e50e0f ArmPkg/CompilerIntrinsicsLib ARM: make memset() weak again
After the recent update of CompilerIntrinsicsLib, our memset() is no
longer emitted as a weak symbol. On ARM, this may cause problems when
combining this library with another library that supplies memset() [e.g.,
CryptoPkg/IntrinsicLib], due to the fact that the object also supplies
the __aeabi_memXXX entry points, which can only be satisfied by this
object. So make our memset() weak again, to let the other implementation
take precedence.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-05 15:38:53 +01:00
Ard Biesheuvel 0b09c212a8 ArmPkg/BaseMemoryLibStm: implement new IsZeroBuffer() API function
BaseMemoryLib has recently been extended with an API function
IsZeroBuffer(), so copy the default implementation into BaseMemoryLibStm
as well.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-02 20:10:49 +01:00
Ard Biesheuvel a548a5421f ArmPkg/BaseMemoryLibStm: implement new IsZeroGuid() API function
BaseMemoryLib has recently been extended with an API function
IsZeroGuid(), so copy the default implementation into BaseMemoryLibStm
as well.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-02 20:10:38 +01:00
Ard Biesheuvel 5322ee484b ArmPkg: remove BaseMemoryLibVstm implementation of BaseMemoryLib
The BaseMemoryLibVstm implementation of BaseMemoryLib is ARM only, uses
the NEON register file despite the fact that the UEFI spec does not allow
it, and is currently not used anywhere. So remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-01 15:03:00 +01:00
Ard Biesheuvel a0cf6b8d93 ArmPkg/CompilerIntrinsicsLib: replace memcpy and memset with C code
This replaces the various implementations of memset and memcpy,
including the ARM RTABI ones (__aeabi_mem[set|clr]_[|4|8]) with
a single C implementation for each. The ones we have are either not
very sophisticated (ARM), or they are too sophisticated (memcpy() on
AARCH64, which may perform unaligned accesses) or already coded in C
(memset on AArch64).

The Tianocore codebase mandates the explicit use of its SetMem() and
CopyMem() equivalents, of which various implementations exist for use
in different contexts (PEI, DXE). Few compiler generated references to
these functions should remain, and so our implementations in this BASE
library should be small and usable with the MMU off.

So replace them with a simple C implementation that builds correctly
on GCC/AARCH64, CLANG/AARCH64, GCC/ARM, CLANG/ARM and RVCT/ARM.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-01 14:51:18 +01:00
Ard Biesheuvel 22b080c78c ArmPkg/SemihostLib: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:40:52 +02:00
Ard Biesheuvel 903e31242d ArmPkg/CompilerIntrinsicsLib: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections. Note that in some cases, various entry points
refer to different parts of the same routine, so in those cases,
the files have been left untouched.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:40:51 +02:00
Ard Biesheuvel 7589d9dbcf ArmPkg/BaseMemoryLibVstm: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel 8ca934aab5 ArmPkg/BaseMemoryLibSm: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel 86a4d91bda ArmPkg/ArmSmcLib: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel e4d37ada01 ArmPkg/ArmMmuLib: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel 0efaa42f6e ArmPkg/ArmLib: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel de656e666c ArmPkg/ArmHvcLib: switch to ASM_FUNC() asm macro
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel 5e32710023 ArmPkg/ArmSmcLibNull: move to generic C implementation
The C language is powerful enough to implement a function that does
absolutely nothing, so there is no need to resort to implementations
in assembler for various toolchains/architectures.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel 2b47cdc936 ArmLib: remove ArmReplaceLiveTranslationEntry() implementation
The function ArmReplaceLiveTranslationEntry() has been moved to
ArmMmuLib, so remove the old implementation from ArmLib.

Note that the new implementation was not exported from the object file,
and so references to it were satisfied by the old version residing in
ArmLib. Since we are removing that one, we need to export the new one
at the same time to prevent the linker from bailing with undefined
reference errors.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11 12:29:31 +02:00
Ard Biesheuvel f8c51389c6 ArmPkg/CompilerIntrinsicsLib: make the default memset() weak
The ARM compiler intrinsics library defines __aeabi_memset() and
memset() in the same object, which means that both will be pulled
in if either is referenced.

The IntrinsicLib in CryptoPkg defines its own, preferred memset(),
which may clash with our memset(). So make our version weak.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-05 16:32:36 +02:00
Ard Biesheuvel 59ceaa0a87 ArmPkg/ArmSoftFloatLib: disable LTO build for GCC
Building ArmSoftFloatLib with LTO results in errors like

  .../bin/ld: softfloat.obj: plugin needed to handle lto object
  .../bin/ld: __aeabi_dcmpge.obj: plugin needed to handle lto object
  .../bin/ld: __aeabi_dcmplt.obj: plugin needed to handle lto object
  .../bin/ld: internal error ../../ld/ldlang.c 6299

This library is only linked by OpensslLib at the moment, and only
marginally used at runtime, so just disable LTO for it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-05 16:32:35 +02:00
Ard Biesheuvel e1458aaded ArmPkg: add prebuilt glue binaries for GCC5 LTO support
GCC in LTO mode interoperates poorly with non-standard libraries that
provide implementations of compiler intrinsics such as memcpy/memset
or the stack protector entry points. Such libraries need to be built
in non-LTO mode, and then referenced explicitly on the linker command
line using a -plugin-opt=-pass-through=-lxxx linker option.

However, if these intrinsics are also referenced directly, the LTO
version of the code will be pulled in, and will happily satisfy all
other references to the same symbol.

So add a pair of glue libraries, for ARM and AARCH64, that reference
the known intrinsics. Since the binaries live under ArmPkg directly,
we can reference them in tools_def.txt. Under LD garbage collection,
the object itself will be pruned, and so will the intrinsics that end
up unused by the module.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-02 10:53:57 +02:00
Supreeth Venkatesh 07783fdd67 ArmPkg/Library: Add ArmReadSctlr for AArch64
ArmLib defines a prototype for the ArmReadSctlr() function, but the
AArch64 implementation is missing. So add it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
[ardb: update commit log]
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-01 14:07:17 +02:00
Ard Biesheuvel 87bcfe1303 ArmPkg/ArmMmuLib: add PEI specific version of ArmMmuLib
This introduces a special version of ArmMmuLib for PEIMs that takes care
only to perform cache maintenance on the live entry replacement routine
if the module is not executing in place. Not only is such cache maintenance
unnecessary in that case, it may be actively harmful on some systems that
fail to tolerate cache maintenance operations on NOR flash regions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-07-07 14:36:45 +02:00
Ard Biesheuvel 5db1cce145 ArmPkg ArmVirtPkg MdeModulePkg: switch to separate ArmMmuLib
Switch all users of ArmLib that depend on the MMU routines to the new,
separate ArmMmuLib. This needs to occur in one go, since the MMU
routines are removed from ArmLib build at the same time, to prevent
conflicting symbols.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-07-07 14:33:47 +02:00
Ard Biesheuvel d7f03464b2 ArmPkg: introduce base ArmMmuLib implementation
This base library encapsulates the MMU manipulation routines that have been
factored out of ArmLib. The functionality covers initial creation of the 1:1
mapping in the page tables, and remapping regions to change permissions or
cacheability attributes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-07-07 14:33:47 +02:00
Ard Biesheuvel f9ebccec09 ArmPkg/DefaultExceptionHandlerLib: put ASSERT (FALSE) last
Putting DEBUG () code after an ASSERT (FALSE) statement is not very
useful, since the code will be unreachable on DEBUG builds and compiled
out on RELEASE builds. So move the ASSERT () statement after it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-07-01 13:24:25 +02:00
Ard Biesheuvel 469e1e1e42 ArmPkg/ArmLib: avoid cache maintenance in PEIMs when executing in place
On some platforms, performing cache maintenance on regions that are backed
by NOR flash result in SErrors. Since cache maintenance is unnecessary in
that case, create a PEIM specific version that only performs said cache
maintenance in its constructor if the module is shadowed in RAM. To avoid
performing the cache maintenance if the MMU code is not used to begin with,
check that explicitly in the constructor.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-06-15 17:23:09 +02:00
Ard Biesheuvel c976f9cb7d ArmPkg/PlatformBootManagerLib: implement new generic version
This implements the platform glue for the new generic BDS implementation.
It is based on the ArmVirtQemu version, with the QEMU references removed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-12 13:56:50 +02:00
Ard Biesheuvel cf580da1bc ArmPkg/ArmLib: don't invalidate entire I-cache on range operation
Instead of cleaning the data cache to the PoU by virtual address and
subsequently invalidating the entire I-cache, invalidate only the
range that we just cleaned. This way, we don't invalidate other
cachelines unnecessarily.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-12 13:53:08 +02:00
Ard Biesheuvel d1ec2b2f78 ArmPkg/AArch64Mmu: don't let table entries inherit XN permission bits
When we split a block entry into a table entry, the UXN/PXN/XN permission
attributes are inherited both by the new table entry and by the new block
entries at the next level down. Unlike the NS bit, which only affects the
next level of lookup, the XN table bits supersede the permissions of the
final translation, and setting the permissions at multiple levels is not
only redundant, it also prevents us from lifting XN restrictions on a
subregion of the original block entry by simply clearing the appropriate
bits at the lowest level.

So drop the code that sets the UXN/PXN/XN bits on the table entries.

Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:44:40 +02:00
Ard Biesheuvel b64e44cc09 ArmPkg/ArmDmaLib: assert that consistent mappings are uncached
DmaMap () only allows uncached mappings to be used for creating consistent
mappings with operation type MapOperationBusMasterCommonBuffer. However,
if the buffer passed to DmaMap () happens to be aligned to the CWG, there
is no need for a bounce buffer, and we perform the cache maintenance
directly without ever checking if the memory attributes of the buffer
adhere to the API.

So add some debug code that asserts that the operation type and the memory
attributes are consistent.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:44:40 +02:00
Ard Biesheuvel 32e5fb76e5 ArmPkg/ArmDmaLib: do not remap arbitrary memory regions as uncached
In the DmaMap () operation, if the region to be mapped happens to be
aligned to the Cache Writeback Granule (CWG) (whose value is typically
64 or 128 bytes and 2 KB maximum), we remap the memory as uncached.

Since remapping memory occurs at page granularity, while the buffer and the
CWG may be much smaller, there is no telling what other memory we affect
by doing this, especially since the operation is not reverted in DmaUnmap().

So remove the remapping call.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:44:40 +02:00
Ard Biesheuvel a24f7d6680 ArmPkg/ArmDmaLib: reject consistent DMA mappings of cached memory
DmaMap () operations of type MapOperationBusMasterCommonBuffer should
return a mapping that is coherent between the CPU and the device. For
this reason, the API only allows DmaMap () to be called with this operation
type if the memory to be mapped was allocated by DmaAllocateBuffer (),
which in this implementation guarantees the coherency by using uncached
mappings on the CPU side.

This means that, if we encounter a cached mapping in DmaMap () with this
operation type, the code is either broken, or someone is violating the
API, but simply proceeding with a double buffer makes no sense at all,
and can only cause problems.

So instead, actively reject this operation type for cached memory mappings.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:44:39 +02:00
Ard Biesheuvel 885d57ef09 ArmPkg/ArmDmaLib: interpret GCD attributes as a bit field
Comparing a GCD attribute field directly against EFI_MEMORY_UC and
EFI_MEMORY_WT is incorrect, since it may have other bits set as well
which are not related to the cacheability of the region. So instead,
test explicitly against the flags EFI_MEMORY_WB and EFI_MEMORY_WT,
which must be set if the region may be mapped with cacheable attributes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:44:39 +02:00
Ard Biesheuvel 80e5a33da1 ArmPkg/ArmDmaLib: consistently use 'gCacheAlignment - 1' as alignment mask
We manage to use both an AND operation with 'gCacheAlignment - 1' and a
modulo operation with 'gCacheAlignment' in the same compound if statement.
Since gCacheAlignment is a global of which the compiler cannot guarantee
that it is a power of two, simply use the AND version in both cases.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:44:27 +02:00
Ard Biesheuvel e55f8c73b6 ArmPkg/ArmDmaLib: deal with NULL return value of UncachedAllocatePages ()
The allocation function UncachedAllocatePages () may return NULL, in
which case our implementation of DmaAllocateBuffer () should return
EFI_OUT_OF_RESOURCES rather than silently ignoring the NULL value and
returning EFI_SUCCESS.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-10 14:38:59 +02:00
Ard Biesheuvel 9f64a83484 ArmPkg/DefaultExceptionHandlerLib: fix typo
Replace : with ; which was changes accidentally.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-05-09 17:28:05 +02:00
Ard Biesheuvel cd82e330bb ArmPkg/DefaultExceptionHandlerLib: add stack dump to exception handling code
This adds a partial stack dump (256 bytes at either side of the stack
pointer) to the CPU state dumping routine that is invoked when taking an
unexpected exception. Since dereferencing the stack pointer may itself
fault, ensure that we don't enter the dumping routine recursively.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-09 17:25:52 +02:00
Ard Biesheuvel 1549fb607b ArmPkg/DefaultExceptionHandlerLib: use deadloop rather than ASSERT
The default exception handler, which is essentially the one that is invoked
for unexpected exceptions, ends with an ASSERT (FALSE), to ensure that
execution halts after dumping the CPU state. However, ASSERTs are compiled
out in RELEASE builds, and since we simply return to wherever the ELR is
pointing, we will not make any progress in case of synchronous aborts, and
the same exception will be taken again immediately, resulting in the string
'Exception at 0x....' to be printed over and over again.

So use an explicit deadloop instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-09 17:24:52 +02:00
Ard Biesheuvel 61b02ba1f2 ArmPkg/AArch64Mmu: disable MMU during page table manipulations
On ARM, manipulating live page tables is cumbersome since the architecture
mandates the use of break-before-make, i.e., replacing a block entry with
a table entry requires an intermediate step via an invalid entry, or TLB
conflicts may occur.

Since it is not generally feasible to decide in the page table manipulation
routines whether such an invalid entry will result in those routines
themselves to become unavailable, use a function that is callable with
the MMU off (i.e., a leaf function that does not access the stack) to
perform the change of a block entry into a table entry.

Note that the opposite should never occur, i.e., table entries are never
coalesced into block entries.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
2016-04-14 18:01:52 +02:00
Heyi Guo 40e06cad13 ArmPkg/AArch64Mmu: Fix XN attribute for device memory
Now XN attribute will be set automatically if the region is declared
as device memory. However, the function ArmMemoryAttributeToPageAttribute
is to get attribute for block and page descriptors, not for table
descriptors, so attribute TT_TABLE_*XN does not really take effect.

Need to use TT_*XN_MASK instead.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-04-14 11:38:36 +02:00
Evan Lloyd f75cda7702 ArmPkg/ArmArchTimerLib: correct typos
Some minor typographical problems were noticed during previous commits.
This change corrects those, and contains no functional modifications.
The changes are in comments, and one diagnostic message.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-04-01 17:19:24 +02:00
Sami Mujawar b843b3730d ArmPkg/ArmArchTimerLib: fix unused variable in RELEASE builds
The TimerFreq variable in the TimerConstructor() is unused in RELEASE
builds since ASSERTs are then disabled.
The only use of the variable (in the ASSERT) is replaced by a direct
invocation of the function previously used to set it.

NOTE: The build tools suppress warnings of this using compiler options
eg. -Wno-unused-but-set-variable for GCC toolchain or
    --diag_suppress=550 for RVCT toolchain.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-04-01 17:14:47 +02:00
Sami Mujawar 96a80ae3ce ArmPkg/ArmArchTimerLib: add GetTimeInNanoSecond() to ArmArchTimerLib
FirmwarePerformanceDxe.c utilizes the Timer Library function
GetTimeInNanoSecond() which was not implemented by the ArmArchTimerLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-04-01 15:52:17 +02:00
Sami Mujawar cbdece1769 ArmPkg/ArchArmTimerLib: refactor MultU64xN and TimerFreq definitions
This refactors some timer code to define MultU64xN as a preprocessor
symbol rather than a function pointer, and to factor out the code that
obtains the timer frequency into GetPlatformTimerFreq ().

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>

Contributed-under: TianoCore Contribution Agreement 1.0
[ard.biesheuvel: split off from 'add GetTimeInNanoSecond() to ArmArchTimerLib']
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-04-01 15:52:16 +02:00
Leendert van Doorn f0bbcdf80d ArmPkg|EmbeddedPkg: make PcdCpuVectorBaseAddress 64 bits wide
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-25 07:17:53 +01:00
Ard Biesheuvel b5d89de167 ArmPkg/AArch64Mmu: use correct AP[] bits in ArmClearMemoryRegionReadOnly
The function ArmClearMemoryRegionReadOnly() was supposed to undo the
effect of ArmSetMemoryRegionReadOnly(), but instead, it sets the permissions
to EL0-no access, EL1-read-only. Since the EL0 bit should be 1 to align
with EL2/3 (where the bit is SBO), use TT_AP_RW_RW instead, which makes the
entry read-write for EL0 when executing at EL1, and read-write for all other
levels.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-03-22 17:32:25 +01:00
Ard Biesheuvel 1b02a38329 ArmPkg/ArmExceptionLib: reimplement register stack/unstack routines
This replaces the somewhat opaque preprocessor based stack/unstack macros
with open coded ldp/stp sequences to preserve the interrupted context
before handing over to the exception handler in C.

This removes various arithmetic operations on the stack pointer, and
reduces the exception return critical section to its minimum size (i.e.,
the bare minimum required to populate the ELR and SPSR registers and invoke
the eret).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22 14:48:06 +01:00
Ard Biesheuvel 5d7238cae8 ArmPkg/ArmExceptionLib: avoid indirect call if using vector table in place
If we are using the vector table in place, there is no need to make an
indirect call to the common handler routine from the vector table entries,
so just use a straight branch instruction in that case.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22 14:39:02 +01:00
Ard Biesheuvel 8a771a2e39 ArmPkg/ArmExceptionLib: make build time define visible to the compiler
The global gArmRelocateVectorTable is a build time constant, but due to
its external linkage and lack of constness, the compiler does not see that.
So turn it into a static boolean, and at the same time, make the function
CopyExceptionHandlers() (which is only called if gArmRelocateVectorTable is
set) static as well, so that the compiler can eliminate it completely if
we are using the vector table in place.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22 14:39:02 +01:00
Ard Biesheuvel 2187f9a052 ArmPkg/ArmExceptionLib: don't restore ESR and FAR upon exception return
ESR and FAR are populated by the hardware upon exception entry, and
describe the exception, not the interrupted context. So there is no point
in restoring their values before returning from the exception.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22 14:39:02 +01:00
Ard Biesheuvel 02e261c3f8 ArmPkg/ArmExceptionLib: stack FPSR on common path
We have three code paths to stack/unstack the exception context, one for
each of EL3, EL2 and EL1. However, they all access the same copy of FPSR
so move that access to the common path.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22 14:39:02 +01:00
Ard Biesheuvel 0dbbaa5573 ArmPkg/ArmExceptionLib: fold exception handler prologue into vector table
Unlike the AArch32 vector table, which has room for a single instruction
for each exception type, the AArch64 exception table has 128 byte slots,
which can easily hold the shared prologues that are emitted out of line.

So refactor this code into a single macro, and expand it into each vector
table slot. Since the address of the command handler entry point is no
longer patched in by the C code, we can just emit the literal into each
vector entry directly.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
2016-03-22 14:39:02 +01:00
Cohen, Eugene 2939c778a3 ArmPkg: ARM/AArch64 implementation of CpuExceptionHandlerLib
Introduce ARM and AArch64 instances of the CpuExceptionHandlerLib which
provides exception handling and registration of handlers regardless of
execution phase.

Two variants of the ArmExceptionLib are provided: one where exception
handlers reside within the module (meeting appropriate architectural
alignment requirements for the vector table) and another one that will
relocate a copy of thee xception handlers to an address specified by
PcdCpuVectorBaseAddress. The ArmRelocateExceptionLib is intended for use
in cases where ArmExceptionLib is too large for the application
(uncompressed XIP images) as driven by the vector table alignment padding.

The AArch64 build of this library supports execution at EL1, EL2, and EL3
exception levels.

Tested on ARM, and AArch64 with SEC, DXE Core, and CpuDxe modules.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-16 12:19:58 +01:00
Cohen, Eugene d2bb61a232 ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCR
Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system
register.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-16 12:19:25 +01:00
Evan Lloyd ff1f27c055 ArmPkg: Configure TTBCR register
Architecturally, the TTBCR register value is undefined at reset for
Non-Secure.
On some platforms the reset value for TTBCR is not zero and
this causes a data abort exception once the MMU is enabled.

This patch configures the TTBCR register to enable translation table
walk using TTBR0.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
2016-03-03 18:23:54 +00:00
Cohen, Eugene 4af3dd80ab ArmPkg: CpuDxe: fix AArch64 interrupt read masks
The AArch64 DAIF bits are different for reading (mrs) versus writing
(msr). The bitmask definitions assumed they were the same causing
incorrect results when trying to determine the current interrupt
state through ArmGetInterruptState.

The logic for interpreting the DAIF read data using the csel instruction
was also incorrect and is fixed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-02-23 12:07:11 +01:00
Cohen, Eugene 82ea9a6b59 ArmPkg: DefaultExceptionHandler fixes for use with DxeCore
Modify the DefaultExceptionHandler (uefi-variant) so it can be used by
DxeCore (via CpuExceptionHandlerLib) where the debug info table is not
yet published at library constructor time.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-02-15 10:37:52 +01:00
Evan Lloyd b2d0e0c51a ArmPkg: Add isb when setting SCR
Some updates to SCR can cause a problem which manifests as an undefined opcode exception.
This may be when a speculative secure instruction fetch happens after the NS bit is set.
An isb is required to make the register change take effect fully.

Contributed-under: Tianocore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Sami Mujawar <Sami.Mujawar@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-02-03 18:42:21 +00:00
Evan Lloyd 2281eb6f48 ArmPkg: Rectify file modes
Problems have been encountered because some of the source files have
execute permission set.  This can cause git to report them as changed
when they are checked out onto a file system with inherited permissions.
This has been seen using Cygwin, MinGW and PowerShell Git.

This patch makes no change to source file content, and only aims to
correct the file modes/permissions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19778 6f19259b-4bc3-4df7-8a09-765794883524
2016-01-30 12:25:59 +00:00
Ard Biesheuvel 0b5d7b6e2e ArmPkg/ArmSoftfloatLib: add missing entry points for RVCT
The RVCT compiler may emit calls to the various __aeabi_c?cmp??
functions, which return their results via the CPU condition flags
C and Z. According to ARM doc IHI 0043D 'Run-time ABI for the ARM
architecture':

    The 3-way comparison functions c*cmple, c*cmpeq and c*rcmple return
    their results in the CPSR Z and C flags. C is clear only if the operands
    are ordered and the first operand is less than the second. Z is set only
    when the operands are ordered and equal.

Add implementations for the double and float variants of the above.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19327 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-17 16:29:23 +00:00
Ard Biesheuvel 46ff196fde ArmPkg/ArmV7Mmu: prefer non shareable memory on non-coherent hardware
Commit SVN r18778 made all mappings of normal memory (inner) shareable,
even on hardware that implements shareability as uncached accesses.
The original concerns that prompted the change, regarding coherent DMA
and virt guests migrating between CPUs, do not apply to such hardware,
so revert to the original behavior in that case.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19285 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 17:31:56 +00:00
Ard Biesheuvel 01627dba09 ArmPkg/ArmSoftfloatLib: restrict -fno-tree-vrp option to GCC46 and GCC47
The -fno-tree-vrp option is not required for GCC 4.8 or later, and is not
supported by CLANG. So restrict its use to GCC 4.6 and 4.7, which are the
oldest versions we support for ARM.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19283 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 15:02:16 +00:00
Ard Biesheuvel 6d2449c1f5 ArmPkg/ArmV7Lib: add CLANG alternative for FPEXC access
The open coded access to co-processor #10 to set FPEXC is not supported
by the CLANG assembler, but the architecturally correct VMSR instruction
is not supported by older binutils. So keep the former unless __clang__
is defined.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19282 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 15:02:07 +00:00
Ard Biesheuvel 19d9bf7725 ArmPkg/CompilerIntrinsicsLib: add GCC version of __aeabi_memset()
CLANG for ARM may emit calls to __aeabi_memset(), which is subtly different
from the default memset() [arguments 2 and 3 are reversed]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19281 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 15:01:58 +00:00
Ard Biesheuvel 1a0db79125 ArmPkg: use unified asm syntax for CLANG
The CLANG assembler does not support the legacy, non-unified assembler syntax,
i.e., it does not support the reordering of the condition suffixes with the
increment/decrement before/after or byte/word suffixes, and it does not
recognize the 'empty descending' (ED) suffix at all. So move to the unified
syntax, and replace 'empty descending' with 'decrement after' or 'increment
before' as appropriate.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19280 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 15:01:42 +00:00
Eugene Cohen b7de7e3cab ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU
This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to
flush the data cache only to the point of unification (PoU). This improves
performance and also allows invalidation in scenarios where it would be
inappropriate to flush to the point of coherency (like when executing code
from L2 configured as cache-as-ram).

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>

Added AARCH64 and ARM/GCC implementations of the above.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 15:58:53 +00:00