Replace the uncached memory mapping of the framebuffer with a write-
combining one. This improves performance, and avoids issues with
unaligned accesses and DC ZVA instructions performed by the accelerated
memcpy/memset routines.
Instead of manipulating the memory attributes directly, use the
SetMemorySpaceAttributes() DXE services, which validates the attributes
against the capabilities of the region before making the actual change.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Replace the uncached memory mapping of the framebuffer with a write-
combining one. This improves performance, and avoids issues with
unaligned accesses and DC ZVA instructions performed by the accelerated
memcpy/memset routines.
Instead of manipulating the memory attributes directly, use the
SetMemorySpaceAttributes() DXE services, which validates the attributes
against the capabilities of the region before making the actual change.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
When we fail to modify the memory attributes for the VRAM allocation,
the allocation - which was made using AllocatePages() - is freed using
FreePool(). This is incorrect by itself, but it masks a second bug, i.e.,
that the address of the allocation is not in VramBaseAddress but in
*VramBaseAddress. So fix both issues.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
When we fail to modify the memory attributes for the VRAM allocation,
the allocation - which was made using AllocatePages() - is freed using
FreePool(). This is incorrect by itself, but it masks a second bug, i.e.,
that the address of the allocation is not in VramBaseAddress but in
*VramBaseAddress. So fix both issues.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
The VRAM of the PL111 on the FVP Base/Foundation models is described as
device memory rather than uncached memory, which is not an accurate
description of the nature of the region (i.e., a framebuffer), and may
result in problems when using accelerated string routines to access the
region, since this may legally involve unaligned accesses or DC ZVA
instructions, which are not allowed on device mappings.
So split of the 8 MB VRAM region into a separate region, and map it using
memory attributes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
ARM TZASC-380 IP provides a mechanism to split memory regions being
protected via it into eight equal-sized sub-regions. A bit-setting
allows the corresponding subregion to be disabled.
Several NXP/FSL SoCs support the TZASC-380 IP block and allow
the DDR connected via the TZASC to be partitioned into regions
having different security settings and also allow subregions
to be disabled.
This patch enables this support and can be used for SoCs which
support such a partition of DDR regions.
Details of the 'subregion_disable' register can be viewed here:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0431c/CHDIGDCI.html
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@nxp.com>
[bhupesh.linux@gmail.com : Added gmail ID as NXP one is no longer valid]
Signed-off-by: Bhupesh Sharma <bhupesh.linux@gmail.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
The number of memory map entries used exceeded the allocated count,
thereby causing memory corruption.
Fixed the number of Virtual Memory Map Descriptors allocated in
describing the RTSM Memory Map. Also added an assert to confirm
that the descriptor count has not been exceeded, in the hope that it may
help highlight the problem should a new entry be added.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
This change is purely cosmetic, with no functional impact, and only
exists to isolate cosmetic changes from a functional fix.
Some indentation is adjusted.
Overlength lines are re-flowed.
alignment on = is adjusted as some lines exceeded 80 columns.
if statement converted to conditional assignment.
Redundant re-calculation of CacheAttributes removed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
On ARM systems, mapping normal memory as device memory may have unintended
side effects, given that unaligned accesses or loads and stores with special
semantics (e.g., load/store exclusive) may fault or may not work as expected.
Similarly, DC ZVA instructions are only supported on normal memory, not
device memory.
So remove the EFI_MEMORY_UC attribute that we set by default on system RAM.
If any region requires this attribute, it is up to the driver to set this
attribute, and to ensure that no offending operations are performed on it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
According to the ACPI 6.0/6.1 spec, the physical base address of GICC,
GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC
base address PCDs to 64-bit, and fix up all users.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
The RVCT .asm files include AsmMacroIoLib.h only for the definition of
LoadConstantToReg (), which makes it tedious to make change to that file
without the risk of making the RVCT assembler unhappy. So simply replace
LoadConstantToReg() with mov32, which does the right thing in all cases.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
We can refer to gArmMpCoreInfoPpiGuid directly if we declare it under
[Ppis] in the library's .inf so there is no need to copy it into a
module local variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19243 6f19259b-4bc3-4df7-8a09-765794883524
We can refer to gArmMpCoreInfoPpiGuid directly if we declare it under
[Ppis] in the library's .inf so there is no need to copy it into a
module local variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19242 6f19259b-4bc3-4df7-8a09-765794883524
We can refer to gArmMpCoreInfoPpiGuid directly if we declare it under
[Ppis] in the library's .inf so there is no need to copy it into a
module local variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19241 6f19259b-4bc3-4df7-8a09-765794883524
Some users of this library (i.e., FVP-AArch64 and RTSM-A15_MPCore)
may be built to execute straight from NOR flash. Since device mappings
should have the XN attribute set (according to the architecture), mapping
the NOR flash as a device may prevent it from being executable.
Since the NOR flash DXE driver is perfectly capable of setting the correct
attributes for the region it needs to write to, and since we will be
executing from DRAM by that time anyway, we can simply map the NOR flash
as normal memory initially.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18890 6f19259b-4bc3-4df7-8a09-765794883524
These are no longer used by any platform in the tree, nor are they
of any significance to any out of tree platforms.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18571 6f19259b-4bc3-4df7-8a09-765794883524
This adds a ArmPlatformSysConfigLib implementation that is usable by
DXE_RUNTIME_DRIVER modules. Since the system registers that this library
encapsulates are not usable at runtime, this driver allows access to
those registers only at boot time.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17925 6f19259b-4bc3-4df7-8a09-765794883524
Since ArmVExpressSysConfigLib cannot be supported at runtime, restrict
its use to the types of modules that are currently using it legally.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17382 6f19259b-4bc3-4df7-8a09-765794883524
There are three FVP variants for the Base and Foundation models:
- model with GICv2 legacy memory map (same location as the Versatile Express model)
- model with GICv2 and Base model memory map
- model with GICv3 and Base model memory map
The new code detects the variants to load the appropriate device tree.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16932 6f19259b-4bc3-4df7-8a09-765794883524
Add a function to ArmVExpressDxe to identify the current platform we
are running on. This includes ARM32 and AArch64 models and hardware.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16931 6f19259b-4bc3-4df7-8a09-765794883524
Some AArch64 platforms have RAM and flash devices >4GB.
Update some additional Pcd entries to 64-bit, and change
the corresponding PcdGet32 calls to PcdGet64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
This PCD has been replaced by ArmPlatformIsPrimaryCore() function.
Althrough this PCD is still used in some occasions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16026 6f19259b-4bc3-4df7-8a09-765794883524
Replace tabs by spaces for indentation to comply to EDK2 coding standards.
Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf",
"*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg,
BeagleBoardPkg or Omap35xxPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
- Variable may be used before being set
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15719 6f19259b-4bc3-4df7-8a09-765794883524
AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a
AND with the immediate inverted, but Clang's integrated assembler emits an
error.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
This ensures the .type directive is used to mark them as function symbols
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
Some non-GCC toolchain might support the GNU assembly language.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
The FVP Foundation model has additional DRAM regions at 0x08_8000_0000.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15464 6f19259b-4bc3-4df7-8a09-765794883524
The FVP Base and Foundation models have additional DRAM regions at
0x08_8000_0000.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15461 6f19259b-4bc3-4df7-8a09-765794883524
This code is only specific to the ARM Versatile Express hardware board.
There is no concept of logic tile on the FVP model.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15460 6f19259b-4bc3-4df7-8a09-765794883524
The System Memory region might be out of the 32-bit memory space.
This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:
- # System Memory (2GB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
EFI Shell and Linux kernel boot successfully.
Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
- Used correct PCD
- Implement the function for AArch64, BeagleBoard, CTA15A7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14937 6f19259b-4bc3-4df7-8a09-765794883524
If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe
(waiting for the memory to be initialized) as the instruction is still in the remapped
flash region at 0x0 to make them jumping into the C-code which lives in the NOR1 at 0x44000000 before
the region 0x0 is remapped as DRAM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14910 6f19259b-4bc3-4df7-8a09-765794883524
The FVP Base Model has GICv3 support.
UEFI SEC does limited configuration of GICv3 if present. This is required for Linux to use GICv3.
UEFI itself uses the GICv3 in legacy mode (GICv2).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14824 6f19259b-4bc3-4df7-8a09-765794883524
This value was missing from the switch on 'ResetType'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14583 6f19259b-4bc3-4df7-8a09-765794883524
- Setting DVI fails on VE models. The FVP models behave the same.
These have updated SYS ID numbers and they need to be added to the
driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14564 6f19259b-4bc3-4df7-8a09-765794883524
ARM Versatile Express TC2 Core Tile has two profiles: the 1GB DRAM core tile or
the 2GB DRAM core tile profiles.
By default UEFI assumes, it is the 1GB core tile. In case of 2GB DRAM it declares
this additional 1GB resource system memory to UEFI. But the previous code did
not map this memory in the MMU Page Table.
So, the memory was allocatable by UEFI modules, but was not accessible by the CPU
(because not mapped).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <Leif.Lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14449 6f19259b-4bc3-4df7-8a09-765794883524
LibResetSystem was performing a cold reboot for both reboot and
shutdown.
This patch updates LibResetSystem to pass SYS_CFG_SHUTDOWN to the
microcontroller when called wit EfiResetShutdown.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14438 6f19259b-4bc3-4df7-8a09-765794883524
This function allows platform to do any specific actions prior to
the start the PEI phase.
For instance, this function could be used by some platforms to initialize clocks that
are required at the early stage of the PEI phase.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14347 6f19259b-4bc3-4df7-8a09-765794883524
Ard Biesheuvel
Bhupesh Sharma
Sami Mujawar
Evan Lloyd
Dennis Chen
Olivier Martin
Leif Lindholm
Ronald Cron
Harry Liebel
Brendan Jackman
Ryan Harkin
oliviermartin