Commit Graph

611 Commits

Author SHA1 Message Date
Jeff Fan 91e3003c97 UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:42 +08:00
Jeff Fan c2aa191b50 UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:39 +08:00
Jeff Fan fed6c37b4a UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:35 +08:00
Jeff Fan e108c3f64d UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:32 +08:00
Jeff Fan a73ab08301 UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:28 +08:00
Jeff Fan adf109740f UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:24 +08:00
Jeff Fan e43a671439 UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:20 +08:00
Jeff Fan a6b7bc3c2f UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:16 +08:00
Jeff Fan 800a651d6d UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:13 +08:00
Jeff Fan 7de98828b7 UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:08 +08:00
Star Zeng b10d5ddc03 UefiCpuPkg/PiSmmCpuDxeSmm: Consume PcdAcpiS3Enable to control the code
if PcdAcpiS3Enable is disabled, then skip S3 related logic.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-09-01 08:18:59 -07:00
Star Zeng 0bdc9e75c0 UefiCpuPkg/PiSmmCpuDxeSmm: Move S3 related code to CpuS3.c
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2016-09-01 08:18:59 -07:00
Star Zeng ca98f60382 UefiCpuPkg/CpuS3DataDxe: Consume PcdAcpiS3Enable to control the code
If PcdAcpiS3Enable is disabled, then return an EFI_UNSUPPORTED
error which forces the module to be unloaded.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-09-01 08:18:59 -07:00
Jeff Fan 3ed4e502b5 UefiCpuPkg/MpInitLib: Don't allocate reset vector in Exit Boot Service
In Exit Boot Services callback function, we cannot use allocate memory services
because it may change the memory map that has been gotten by OS.

This fix is not to allocate reset vector buffer after SaveRestoreFlag is set to
TRUE in MpInitExitBootServicesCallback(). Instead AllocateResetVector() will use
the previous allocated buffer address and save the contents before copying reset
vector code. At the same time, FreeResetVector() will restore original contents
after if SaveRestoreFlag is TRUE.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:55 +08:00
Jeff Fan 42c37b3b33 UefiCpuPkg/MpInitLib: Move two functions location
Just move BackupAndPrepareWakeupBuffer() and RestoreWakeupBuffer() from
PeiMpLib.c to MpLib.c.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:50 +08:00
Jeff Fan b31c1ad11e UefiCpuPkg/MpInitLib: Fix function header comments typo
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:46 +08:00
Jeff Fan d11f10d1e0 UefiCpuPkg/MpInitLib: Rename EndOfPeiFlag to SaveRestoreFlag
It will be used by DxePeiLib also.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:41 +08:00
Jeff Fan 5183fb3736 UefiCpuPkg/MpInitLib: Move allocating reserved memory for AP loop code
In Exit Boot Services callback function, we cannot use allocate memory services
because it may change the memory map that has been gotten by OS.

This fix is to move allocating reserved memory for AP loop code to
InitMpGlobalData() and save the memory address in one global variable.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:37 +08:00
Jeff Fan c119221060 UefiCpuPkg/MpInitLib: Move timeout delay to WakupAp()
After sending the 1st broadcast INIT-SIPI-SIPI, BSP will collect APs count after
one specified timeout delay. However, WakupAp() will restore reset vector
immediately after sending 1st broadcast INIT-SIPI-SIPI. Some processors may not
complete executing reset vector code.

This fix is to move MicroSecondDelay() from CollectProcessorCount() to the place
that is after sending 1st broadcast INIT-SIPI-SIPI and before FreeResetVector()
in WakupAp().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:32 +08:00
Jeff Fan eadf70bdfb UefiCpuPkg/PiSmmCpuDxeSmm: Revert 7503cd70fb
Revert "UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependency"

This reverts commit 7503cd70fb.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
2016-08-19 15:14:28 +08:00
Jeff Fan 8cce3c9a70 UefiCpuPkg/MpInitLib: MicrocodeData used but maybe uninitialized
Cc: Feng Tian <feng.tian@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-19 15:11:01 +08:00
Jeff Fan 7503cd70fb UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependency
PiSmmCpuDxeSmm driver's entry point will get some PCDs supported dynamic type.
In case those PCDs are set as DynamicHii type in platform DSC File, it implies
that EFI Variable Arch protocol is required.

This fix is to add gEfiVariableArchProtocolGuid dependency on PiSmmCpuDxeSmm
driver to make sure those DynamicHii PCDs could be read correctly.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:08:18 +08:00
Jeff Fan f3b91fa04a UefiCpuPkg/CpuDxe: Fixed typo in function header to match PI spec
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:08:01 +08:00
Jeff Fan 0a55f3bd65 UefiCpuPkg/CpuDxe: Remove PcdCpuMaxLogicalProcessorNumber consuming
v5:
  If PcdCpuMaxLogicalProcessorNumber is set to 1 on UP system,
  MpInitLibInitialize() will be invoked. This is one bug, we need to
  call MpInitLibInitialize() always and get the BSP information.
  Just to remove PcdCpuMaxLogicalProcessorNumber() consuming from this
  driver.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:07:16 +08:00
Jeff Fan 39d49a73a5 UefiCpuPkg/CpuDxe: Remove unused codes and files
v5:
  1. Remove unused PcdCpuApStackSize and PcdCpuApInitTimeOutInMicroSeconds.

v4:
  1. Keep GDT table setup to fix IA32 S3 boot issue.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:07:07 +08:00
Jeff Fan 0b9f0dd635 UefiCpuPkg/CpuDxe: Move SetMtrrsFromBuffer() location.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:07:00 +08:00
Jeff Fan 7fadaacd50 UefiCpuPkg/CpuDxe: Consume MpInitLib to produce CPU MP Protocol services
Consume MP Initialize library to produce CPU MP Protocol services to simply the
code.

v4:
  1. Update CpuDxe.c file header to mention it produces CPU Arch protocol.
  2. Update BistData type from UINT32 to EFI_HEALTH_FLAG.
  3. Move some header location from CpuMp.h to CpuDxe.h.

v3:
  1. Move the code Consume MpInitLib APIs to produce CPU MP Protocol from patch
     #40 to this patch.
  2. Add DxeMpInitLib.inf in DSC file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:56 +08:00
Jeff Fan 89fa1bf218 UefiCpuPkg/CpuMpPei: Delete PeiMpServices.c and PeiMpServices.h
Move the code in PeiMpServices.c & PeiMpServices.h to CpuMpPei.c & CpuMpPei.h.

v3:
  1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP
  2. Add PeiMpInitLib.inf in DSC file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:51 +08:00
Jeff Fan 4b0eeef313 UefiCpuPkg/CpuMpPei: Remove unused files and codes
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:43 +08:00
Jeff Fan a1a4c7a467 UefiCpuPkg/CpuMpPei: Consume MpInitLib to produce CPU MP PPI services
Consume MP initialize library to produce CPU MP PPI, it could simply the code.

Add STATIC for some internal functions to avoid build issue with the same
functions name in PeiMpInit instance. They will be removed by the next patch.

v4:
  1. Update BistData type from UINT32 to EFI_HEALTH_FLAGS.

v3:
  1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP
  2. Add PeiMpInitLib.inf in DSC file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:30 +08:00
Jeff Fan 4d3314f694 UefiCpuPkg/MpInitLib: Place APs in safe loop before hand-off to OS
Register Exit Boot Service callback function MpInitExitBootServicesCallback() to
place AP one safe loop before hand-off to OS.

Allocated one reserved memory and copy the AsmRellocateApLoop() code into it. It
could avoid the CPU Dxe driver (located in Boot Service data range) crashed
after Exit Boot Service event.
Place AP into the target Cx-State (specified by PcdCpuApTargetCstate) could save
power if Monitor-mwait feature supported.
In long mode, switch AP into protected mode could let AP not require page table
when executing this safe loop. Page Table (located in Boot Service data range)
may crashed after Exit Boot Service event.

v3:
  1. Rename *RellocateAp* to *RelocateAp*

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:39 +08:00
Jeff Fan 86efe97693 UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupAllAPs()
v4:
  1. Simply the internal function StartupAllAPsWorker()'s function
     header due to it is duplicated with MpInitLibStartupAllAPs().
v3:
  1. Use CamelCase for mStopCheckAllApsStatus and
     CheckAndUpdateApsStatus()

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:31 +08:00
Jeff Fan 20ae57745b UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupThisAP()
v4:
  1. Simply the internal function StartupThisAPWorker()'s comment
     header due to it is duplicated with MpInitLibStartupThisAP().

v3:
  1. Use CamelCase for mStopCheckAllApsStatus and
     CheckAndUpdateApsStatus().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:26 +08:00
Jeff Fan 08085f08ec UefiCpuPkg/MpInitLib: Check APs Status and update APs status
v3:
  1. Use CamelCase for CheckAndUpdateApsStatus().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:22 +08:00
Jeff Fan e37109bcc7 UefiCpuPkg/MpInitLib: Implementation of MpInitLibEnableDisableAP()
v4:
  1. Simply the internal function MpInitLibEnableDisableAP()'s function
     header due to it is duplicated with MpInitLibEnableDisableAP().
v3:
  1. Use CamelCase for mCheckAllAPsEvent, mStopCheckAllApsStatus.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:17 +08:00
Jeff Fan 41be0da59a UefiCpuPkg/MpInitLib: Implementation of MpInitLibSwitchBSP()
v4:
  1. Simply the internal function SwitchBSPWorker()'s comment header
     due to it is duplicated with MpInitLibSwitchBSP().

v3:
  1. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:13 +08:00
Jeff Fan 5c9e099797 UefiCpuPkg/MpInitLib: Implementation of MpInitLibWhoAmI()
v5:
  1. Move checking ProcessNumber before calling GetCpuMpData.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:09 +08:00
Jeff Fan ad52f25edf UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetProcessorInfo()
v5:
  1. Remove (-1) and use the clean code to calculate the Location->Thread
     and Location->Core.

v4:
  1. Update HealthData type from UINT32 to EFI_HEALTH_FLAGS

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:05 +08:00
Jeff Fan 809213a679 UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetNumberOfProcessors()
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:59 +08:00
Jeff Fan 6a2ee2bb63 UefiCpuPkg/MpInitLib: Skip collect processor count if GUIDed HOB exist
If GUIDed HOB mCpuInitMpLibHobGuid exists, we could get the processor count and
processor APICID and Initial APICID from CPU_INFO_IN_HOB. We needn't to delay
for broadcast INIT-SIPI-SIPI results and could improve performance.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:55 +08:00
Jeff Fan 8a2d564b2a UefiCpuPkg/MpInitLib: Sort processor by ascending order of APIC ID
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:49 +08:00
Jeff Fan fe627769c9 UefiCpuPkg/MpInitLib: Enable x2APIC mode on BSP/APs
If x2APIC flag is set, enable x2APIC mode on all APs and BSP. Before we wakeup
APs to enable x2APIC mode, we should wait all APs have finished initialization.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:45 +08:00
Jeff Fan 03434dffb7 UefiCpuPkg/MpInitLib: Send INIT-SIPI-SIPI to get processor count
CollectProcessorCount() will send the 1st INIT-SIPI-SIPI to get processor count
in system.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:40 +08:00
Jeff Fan 96f5920d1d UefiCpuPkg/MpInitLib: Add WakeUpAP()
WakeUpAP() is used to wakeup APs per current ApLoopMode and make sure APs wake
up successfully.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:04 +08:00
Jeff Fan 7c3f2a1253 UefiCpuPkg/MpInitLib: Fill MP_CPU_EXCHANGE_INFO fields
FillExchangeInfoData() is used to fill MP_CPU_EXCHANGE_INFO date exchanged
between C code and assembly code of AP reset vector.

v5:
  1. Reference ApWakeupFunction instead of ApCFunction.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:00 +08:00
Jeff Fan b8b04307eb UefiCpuPkg/MpInitLib: Add ApWakeupFunction() executed by assembly code
ApWakeupFunction() is the first C function executed from AP reset vector. When
APs waken up at the first time, it will sync BSP's MTRR setting and load
microcode on APs and collect APs' BIST information.

When AP tasked finished, it will place APs it one loop specified by ApLoopMode.

v5:
  1. Rename ApCFunction to ApWakeupFunction to meet naming convention.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:54 +08:00
Jeff Fan ed66e0e3f4 UefiCpuPkg/MpInitLib: Allocate AP reset vector buffer under 1MB
In PeiMpInitLib, searching unallocated memory under in
EFI_HOB_TYPE_RESOURCE_DESCRIPTOR hobs to find the memory under 1MB for AP reset
vector. After End of PEI event triggered, we need to restore original the buffer
contents to avoid crash the OS on S3 boot.
In DxeMpInitLib, allocate the memory under 1MB for AP reset vector.

Add helper functions AllocateResetVector()/FreeResetVector() used by WakeupAp().

v3:
  1. Move SetTimer() from Patch #17 to Patch 16.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:50 +08:00
Jeff Fan 963788618b UefiCpuPkg/MpInitLib: Register one period event to check APs status
In DxeMpInitLib, register one period event callback function CheckAPsStatus()
used to check AP Status.

v5:
  1. Introduce AP_CHECK_INTERVAL for adjust AP check timer interval potential.

v3:
  1. Use CamelCase for mCheckAllAPsEvent, mStopCheckAllApsStatus and
     CheckAndUpdateApsStatus().
  2. Move SetTimer() from Patch #17 to Patch 16.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:44 +08:00
Jeff Fan 6dc05093a0 UefiCpuPkg/MpInitLib: Register one End of PEI callback function
In PeiMpInitLib, register End of PEI callback function CpuMpEndOfPeiCallback().

v5:
  1. Add comment block for mMpInitLibNotifyList.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:32 +08:00
Jeff Fan 93ca4c0fd7 UefiCpuPkg/MpInitLib: Save CPU MP Data pointer
In PeiMpInitLib, save CPU MP Data pointer into one local Guided HOB.
In DxeMpInitLib, save CPU MP Data pointer into one global variable.

Add helper functions GetCpuMpData()/SaveCpuMpData().

v5:
  1. Move CPU_INIT_MP_LIB_HOB_GUID from MpLib.c to MpLib.h to make
     all C files visible.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:28 +08:00
Jeff Fan 94f63c765f UefiCpuPkg/MpInitLib: Add MicrocodeDetect() and load microcode on BSP
v4:
  1. ProcessorSignature is updated to CPU_MICROCODE_PROCESSOR_SIGNATURE
     instead of UINT32.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:23 +08:00
Jeff Fan 68cb933071 UefiCpuPkg/MpInitLib: Add CPU_VOLATILE_REGISTERS & worker functions
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored
after APs received INIT IPI.

Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to
save/restore CRx and DRx. It also check if Debugging Extensions supported or
not.

v5:
  1. Add comment block for structure CPU_VOLATILE_REGISTERS.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:19 +08:00
Jeff Fan 03a1a92515 UefiCpuPkg/MpInitLib: Initialize CPU_AP_DATA for CPU APs
Initialize CPU_AP_DATA for CPU APs and add GetApState()/SetApState() helper
functions to get/set AP state.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:15 +08:00
Jeff Fan e59f8f6b36 UefiCpuPkg/MpInitLib: Allocate and initialize memory of MP Data buffer
v5:
  1. Add comment block for enum AP_INIT_STATE and structure CPU_AP_DATA.
  2. Add more comment for structure CPU_INFO_IN_HOB.
  3. Add more clarification in structure _CPU_MP_DATA for those fields
     pass from PEI to DXE.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:59:12 +08:00
Jeff Fan 9ebcf0f400 UefiCpuPkg/MpInitLib: Get ApLoopMode and MointorFilter size
Firstly, get ApLoopMode from PcdCpuApLoopMode. If MonitorMwait feature is not
supported, update ApLoopMode to ApHltLoop. If MonitorMwait feature is supported,
get MointorFilter size by CPUID.[EAX=05H]:EBX.BIT0-15.

v5:
  1. Add comment block for enum AP_LOOP_MODE.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:59:06 +08:00
Jeff Fan f7f85d8360 UefiCpuPkg/MpInitLib: Add MP_ASSEMBLY_ADDRESS_MAP
In MpInitLibInitialize(), invoke AsmGetAddress() to get get assembly functions'
entry addresses and the sizes from returned MP_ASSEMBLY_ADDRESS_MAP structure.

v5:
  1. Add more detailed comments for structure MP_ASSEMBLY_ADDRESS_MAP.

v4:
  1. Add AsmRelocateApLoop information return in AsmGetAddress().

v3:
  1. Rename AsmRellocateApLoop to AsmRelocateApLoop.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:59:01 +08:00
Jeff Fan 7615702169 UefiCpuPkg/MpInitLib: Add AsmRelocateApLoop() assembly code
AsmRelocateApLoop() is used to place APs into MWAIT-loop if MonitorMwait
feature is supported before hand-off to OS, or place APs into HLT-loop if
MonitorMwait feature is not supported.

If the current mode is long mode, we will switch APs to protected mode
before placing APs in MWAIT-loop or HLT-loop. Thus, once APs wakeup from
loop, APs needn't the page table that may be crashed by OS.

v3:
  1. Rename AsmRellocateApLoop to AsmRelocateApLoop.
  2. Fix typo Proteced to Protected.
  3. Fix typo segement to segment
  4. Use word MONITOR instead of mwait-monitor.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:56 +08:00
Jeff Fan 5c66d125ea UefiCpuPkg/MpInitLib: Add EnableExecuteDisable in MP_CPU_EXCHANGE_INFO
EnableExecuteDisable in MP_CPU_EXCHANGE_INFO is used to tell AP reset vector if
enable execute disable feature on APs. This feature should be enabled before CR3
is written.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:48 +08:00
Jeff Fan 8396e2dd30 UefiCpuPkg/MpInitLib: Fix typo and clean up the code
1. Rename NumApsExecutingLoction to NumApsExecutingLocation
2. Update some comments in NASM files.
3. Remove PeiCpuMpData from MP_CPU_EXCHANGE_INFO.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:37 +08:00
Jeff Fan d94e5f6729 UefiCpuPkg/MpInitLib: Add AP assembly code and MP_CPU_EXCHANGE_INFO
Add assembly code for AP reset vector and the definition of MP_CPU_EXCHANGE_INFO
that are used to exchange the data between C code and assembly code when AP wake
up.

v4:
  1. Copy MP_CPU_EXCHANGE_INFO from UefiCpuPkg/CpuMpPei/CpuMpPei.h
  2. Copy MpEqu.inc and MpFuncs.nasm from UefiCpuPkg/CpuMpPei.

v3:
  1. Rename NumApsExecutingLoction to NumApsExecutingLocation
  2. Add whitespace after ; in .nasm file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:30 +08:00
Jeff Fan 3e8ad6bd76 UefiCpuPkg/MpInitLib: Add two instances PeiMpInitLib and DxeMpInitLib
Add two MP Initialize Library instances PeiMpInitLib.inf and DxeMpInitLib.inf
with NULL implementation.

One PeiMpInitLib.inf is consumed by PEI MP driver. Another DxeMpInitLib.inf is
consumed by DXE MP driver.

Place MpInitLibStartupAllAPs()/MpInitLibStartupThisAp()/MpInitLibSwitchBSP()/
MpInitLibEnableDisableAP() into PeiMpLib.c and DxeMpLib.c, because they have
the different implementations and will be updated in latter patches.

v5:
  1. Add back PeiExceptionHandlerLib.inf in UefiCpuPkg.dsc. It is removed
     incorrectly.

v4:
  1. Return EFI_UNSUPPORTED instead of EFI_SUCCESS for NULL implementation of
     all Functions.
  2. Sync MpInitLibxxx functions header updating described in v4 part of Patch
     #4.

v3:
  1. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:07 +08:00
Jeff Fan 87896d03f6 UefiCpuPkg/MpInitLib: Add MP Initialize library class definition
MP Initialize library provides basic functionalities to do APs initialization,
to manage MP information and to wakeup APs to execute AP task.

It could be consumed by CPU MP PEI or DXE drivers to provide CPU MP PPI/Protocol
services.

v4:
  1. MpInitLibGetProcessorInfo():
     Update HealthData type from UINT32 to EFI_HEALTH_FLAGS.
     Add #include <Ppi/SecPlatformInformation.h>
  2. MpInitLibSwitchBSP():
     Return EFI_DEVICE_ERROR instead of EFI_SUCCESS if the calling processor is
     an AP.
  3. MpInitLibStartupThisAP():
     Fix several incorrect references to "APs" to match PI spec.
  4. MpInitLibSwitchBSP() and MpInitLibEnableDisableAP():
     Fix incorrect description on ProcessorNumber.
  5. Trim whitespace at end of line.

v3:
  1. Add whitespace after MpInitLibInitialize
  2. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:57:41 +08:00
Jeff Fan 65b24ada79 UefiCpuPkg/CpuS3DataDxe: Move StartupVector allocation to EndOfDxe()
Currently, we will allocate StartupVector buffer under 1MB at entry point
function. But some modules may allocate some hard code address under 1MB.
For example, LegacyBiosDxe driver tries to manage some legacy range under
640KB.

To avoid the conflicts, we move StartupVector buffer allocation to End Of
DXE event callback function.

v4:
  Update the Context parameter is used as a pointer to AcpiCpuDataEx, then
  we needn't to add the global variable.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:57:32 +08:00
Jeff Fan 5aa2d57667 UefiCpuPkg/MpInitLib: Add microcode definitions defined in IA32 SDM
Add microcode definitions defined in Intel(R) 64 and IA-32 Architectures
Software Developer's Manual Volume 3A, Section 9.11.

v4:
  1. ProcessorSignature type changed to CPU_MICROCODE_PROCESSOR_SIGNATURE
  2. Add pack(1) for structure CPU_MICROCODE_HEADER and
     CPU_MICROCODE_EXTENDED_TABLE.
v3:
  1. Update SDM date to June, 2016
  2. Mention BCD format in CPU_MICROCODE_DATE
  3. Rename ProcessorChecksum to Checksum to match SDM.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:55:25 +08:00
Jeff Fan a742e1865d UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.

Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.

v5:
  1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:54:41 +08:00
Ruiyu Ni 490b048b5a UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-17 13:54:13 +08:00
Hao Wu 72a8abde40 UefiCpuPkg DSC: Add build option to disable deprecated APIs
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated:

[BuildOptions]
  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-08-08 11:00:12 +08:00
Jeff Fan e78a2a49ee UefiCpuPkg/PiSmmCpuDxeSmm: SMM_CPU_DATA_BLOCK is not cleared
The commit 8b9311 changed the zeroing of mSmmMpSyncData of type
SMM_DISPATCHER_MP_SYNC_DATA by the following patch.
 -    ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize);
 +    mSmmMpSyncData->SwitchBsp = FALSE;

mSmmMpSyncDataSize not only includes SMM_DISPATCHER_MP_SYNC_DATA, but
also includes the SMM_CPU_DATA_BLOCK array and one BOOLEAN variable
array as shown here:

  mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) +
       (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) *
       gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;

This patch restores the original ZeroMem() to clear all CPU Sync data.
The commit 8b9311 may cause unexpected behavior.

v2:
  Mentioned CandidateBsp array in comments to make it more accurate.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-07-20 18:50:53 -07:00
Jeff Fan afa7b97154 UefiCpuPkg/CpuDxe: StartupAllAPs in parallel mode
SetMemoryAttributes() will sync BSP's MTRRs settings to all APs by StartupAllAPs
service in serial mode. It may caused much performance impact if there are too
much processors in system. This update is to invoke StartupAllAps in parallel
mode. IA32 SDM does suggest to program MTRRs in parallel mode.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-07-20 11:13:25 +08:00
Jeff Fan 81f560498b UefiCpuPkg/MtrrLib: Add notes for usage by BSP/APs
Except for MtrrSetAllMtrrs(), others services are not suggested to be invoked by
APs because they are not necessary and may invoke DEBUG() to dump MTRR setting.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed: Laszlo Ersek <lersek@redhat.com>
2016-07-20 11:13:02 +08:00
Jeff Fan 9fc34794d6 UefiCpuPkg/MtrrLib: Remove MTRRs display from MtrrSetAllMtrrs()
MtrrSetAllMtrrs() maybe used by APs to sync BSP's MTRR settings. BSP's MTRR
setting should be displayed if EFI_D_CACHE flag is set when MTRR updated. In
MtrrSetAllMtrrs(), it's not necessary to display MTRR setting again due to the
MTRR settings should be always same among BSP/APs. This updating could avoid
APs output MTRR setting at the same time and make display message corrupted.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-07-20 11:12:20 +08:00
Laszlo Ersek 09a85f6eeb UefiCpuPkg/PiSmmCpuDxeSmm: remove superfluous ENDs from NASM source
Commits 28ee581646 and 246cd9085f added these ENDs as part of the
manual conversion from *.asm files. However, the ENDs makes no sense for
NASM. Although they don't break the build, NASM complains about them:

  label alone on a line without a colon might be in error

(This NASM warning category dates back to NASM 0.95, commit
6768eb71d8deb.)

Remove the ENDs.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-07-18 19:23:01 +02:00
Jeff Fan 51773d49de UefiCpuPkg/PiSmmCpuDxeSmm: Clean up CheckFeatureSupported()
Removed EFIAPI and parameter from CheckFeatureSupported() and removed
CheckProcessorFeature() totally.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:58:04 -07:00
Jeff Fan a46a4c90d3 UefiCpuPkg/PiSmmCpuDxeSmm: Check XD/BTS features in SMM relocation
CheckProcessorFeature() invokes MpService->StartupAllAps() to detect
XD/BTS features on normal boot path. It's not necessary and may cause
performance impact, because INIT-SIPI-SIPI must be sent to APs if APs
are in hlt-loop mode. XD/BTS feature detection is moved to
SmmInitHandler() in SMM relocation during normal boot path.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:59 -07:00
Jeff Fan 70a7493d65 UefiCpuPkg/PiSmmCpuDxeSmm: Add SMM S3 boot flag
It will be set to TRUE during S3 resume.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:53 -07:00
Jeff Fan 6c4c15fae6 UefiCpuPkg/PiSmmCpuDxeSmm: Add MemoryMapped in SetProcessorRegister()
REGISTER_TYPE in UefiCpuPkg/Include/AcpiCpuData.h defines a MemoryMapped
enum value.  However support for the MemoryMapped enum is missing from
the implementation of SetProcessorRegister().  This patch adds support
for MemoryMapped type SetProcessorRegister().

One spin lock is added to avoid potential conflict when multiple processor
update the same memory space.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:47 -07:00
Jeff Fan 8b9311b795 UefiCpuPkg/PiSmmCpuDxeSmm: Remove duplicate aligned buffer on S3 path
InitializeMpSyncData() invokes InitializeSmmCpuSemaphores() to allocate an
aligned buffer for all locks and semaphores. However, this function is
invoked on S3 resume path again to reset mSmmMpSyncData. It causes
an additional aligned buffer to be allocated.

This update moves InitializeSmmCpuSemaphores() into
InitializeMpServiceData() that is only invoked on normal boot.
InitializeMpSyncData() is updated to reset the locks/semaphore in
mSmmMpSyncData.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:41 -07:00
Jeff Fan 01beffa7e9 UefiCpuPkg/CpuMpPei: Remove PmodeOffset and LmodeOffset
Remove Pmode(Entry)Offset/Lmode(Entry)Offset and use unified Mode(Entry)Offset
to clean up the definition of MP_ASSEMBLY_ADDRESS_MAP and MP_CPU_EXCHANGE_INFO.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:44:09 +08:00
Jeff Fan 6d98a37159 UefiCpuPkg/CpuMpPei: Remove un-used variables and functions
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:44:04 +08:00
Jeff Fan 9c3d2f9a29 UefiCpuPkg/CpuMpPei: Do not load new GDT table
Do not load the new GDT table and just to use the exiting BSP's GDT table set up
by SEC phase.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:44:00 +08:00
Jeff Fan d1471c0112 UefiCpuPkg/CpuMpPei/X64: Use CodeSegment and DataSegment fields
Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode
MACROs for x64 arch. Switch AP from real mode to long mode directly, so needn't
the CS/DS of protected mode.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:43:36 +08:00
Jeff Fan 249ed12ea0 UefiCpuPkg/CpuMpPei/X64: Remove hard code CPU BIST value
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:41:44 +08:00
Jeff Fan aad5ee4899 UefiCpuPkg/CpuMpPei/Ia32: Use CodeSegment and DataSegment fields
Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode
MACROs.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:41:20 +08:00
Jeff Fan ed04bffe75 UefiCpuPkg/CpuMpPei: Add CodeSegment and DataSegment fields
Added CodeSegment and DataSegment fields in MP_CPU_EXCHANGE_INFO. They are set
to the values of current BSP's CS and DS.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:33:24 +08:00
Jeff Fan 30dc4a49b6 UefiCpuPkg/CpuMpPei: Remove unnecessary variable
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-13 15:42:10 +08:00
Jeff Fan 719ff8cf3e UefiCpuPkg/CpuMpPei: Dump message if microcode signature not matched
Verification microcode signature is one enhancement and not one requirement from
IA32 SDM. This update is just to dump debug message instead of ASSERT() if the
updated microcode signature does not match the loaded microcode signature.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-13 15:41:49 +08:00
Jeff Fan 46fd118219 UefiCpuPkg/CpuMpPei: Skip microcode check/load if it has been loaded
Actually, there is only one microcode region in platform. If microcode has been
loaded, its signature will not be zero and should be loaded successfully.
We needn't to check microcode region and load microcode again. This update is to
skip checking/loading microcode if current microcode signature is not zero.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-13 15:41:14 +08:00
Liming Gao 6f5531d504 UefiCpuPkg CpuMpPei: Update INF to refer to NASM source file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:22 +08:00
Liming Gao 68d37176a5 UefiCpuPkg CpuIo2Dxe: Update INF to refer to NASM source file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:22 +08:00
Liming Gao 9caff8d961 UefiCpuPkg SecCore: Update SecCore inf to refer to nasmb source
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:21 +08:00
Giri P Mudusuru 8ed9ce80a6 UefiCpuPkg: Fix typos in comments
- becasue to because

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 10:29:51 +08:00
Star Zeng 6f9760d88b UefiCpuPkg S3Resume2Pei: Report status code when allocate memory is failed
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-02 12:22:55 +08:00
Laszlo Ersek ef3e20e3ca UefiCpuPkg: fix ASSERT_EFI_ERROR() typos
A number of code locations use

  ASSERT_EFI_ERROR (BooleanExpression)

instead of

  ASSERT (BooleanExpression)

Fix them.

Cc: Jeff Fan <jeff.fan@intel.com>
Reported-by: Gerd Hoffmann <kraxel@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-06-30 17:27:38 +02:00
Liming Gao ad9ec7efad UefiCpuPkg PiSmmCpuDxeSmm: Add nasm source file into INF file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:19 +08:00
Liming Gao ba15b97142 UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmmInit.asm to NASM
Manually convert X64/SmmInit.asm to X64/SmmInit.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:18 +08:00
Liming Gao 9f54832f4b UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiException.asm to NASM
Manually convert X64/SmiException.asm to X64/SmiException.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:18 +08:00
Liming Gao 9a36d4dc3f UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiEntry.asm to NASM
Manually convert X64/SmiEntry.asm to X64/SmiEntry.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:17 +08:00
Liming Gao e1f0eed1b2 UefiCpuPkg PiSmmCpuDxeSmm: Update X64/MpFuncs.nasm
Use 16bit and 32bit assembly code to replace hard code db.

In V2: add 0x67 prefixes to far jumps

Without the a32 modifier under FLAT32_JUMP, and the a16 modifier under
LONG_JUMP, nasm doesn't generate the 0x67 prefixes, and the far jumps
don't work. (For the former, KVM returns an emulation failure. For the
latter, KVM performs a triple fault (guest reboot).) By forcing the 0x67
prefixes we end up with the same machine code as the one open-coded in
"MpFuncs.asm".

This bug breaks S3 resume in the Ia32X64 + SMM_REQUIRE build of OVMF.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-06-28 09:52:16 +08:00
Liming Gao 78cf66eebb UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/MpFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/MpFuncs.asm to X64/MpFuncs.nasm
And, manually update it to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:16 +08:00
Liming Gao 246cd9085f UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmmInit.asm to NASM
Manually convert Ia32/SmmInit.asm to Ia32/SmmInit.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:15 +08:00
Liming Gao 28ee581646 UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiException.asm to NASM
Manually convert Ia32/SmiException.asm to Ia32/SmiException.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:15 +08:00
Liming Gao 63a4f46076 UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiEntry.asm to NASM
Manually convert Ia32/SmiEntry.asm to Ia32/SmiEntry.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:14 +08:00
Liming Gao 55c6d5467e UefiCpuPkg PiSmmCpuDxeSmm: Update Ia32/MpFuncs.nasm
Use 16bit assembly code to replace hard code db.

In V2:
Add 0x67 prefix to far jump

When we enter protected mode, with the far jump still in big real mode,
the JMP instruction not only needs the 0x66 prefix (for 32-bit operand
size), but also the 0x67 prefix (for 32-bit address size). Use the a32
nasm modifier to enforce this.

This bug breaks S3 resume in the Ia32 + SMM_REQUIRE build of OVMF.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-06-28 09:52:13 +08:00
Liming Gao 6997711e7f UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/MpFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/MpFuncs.asm to Ia32/MpFuncs.nasm.
And, manually update it to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:13 +08:00
Liming Gao ac6229a7b8 UefiCpuPkg S3Resume2Pei: Add nasm source file into INF file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:12 +08:00
Liming Gao b3cfdef49e UefiCpuPkg S3Resume2Pei: Convert X64/AsmFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/AsmFuncs.asm to X64/AsmFuncs.nasm.
And, manually add o16 prefix to specify 16bit operation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:12 +08:00
Liming Gao 5104be5fcf UefiCpuPkg S3Resume2Pei: Convert Ia32/AsmFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/AsmFuncs.asm to Ia32/AsmFuncs.nasm.
And, manually add o16 prefix to specify 16bit operation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:11 +08:00
Liming Gao 70f3acf98a UefiCpuPkg CpuExceptionHandlerLib: Add nasm source files into INF files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:10 +08:00
Liming Gao fb501e33c3 UefiCpuPkg CpuExceptionHandlerLib:Convert X64/ExceptionHandlerAsm.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/ExceptionHandlerAsm.asm to X64/ExceptionHandlerAsm.nasm.
Then, manually update nasm to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:10 +08:00
Liming Gao ab7efb664c UefiCpuPkg CpuExceptionHandlerLib:Convert Ia32/ExceptionHandlerAsm.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/ExceptionHandlerAsm.asm to Ia32/ExceptionHandlerAsm.nasm.
Then, manually update nasm to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:09 +08:00
Liming Gao 6bfe841ff2 UefiCpuPkg BaseUefiCpuLib: Add nasm source file in BaseUefiCpuLib.inf
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:08 +08:00
Liming Gao ce3e0a906f UefiCpuPkg BaseUefiCpuLib: Convert X64/InitializeFpu.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/InitializeFpu.asm to X64/InitializeFpu.nasm.
And, manually add .rdata section.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:08 +08:00
Liming Gao f893042d05 UefiCpuPkg BaseUefiCpuLib: Convert Ia32/InitializeFpu.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/InitializeFpu.asm to Ia32/InitializeFpu.nasm.
And, manually add .rdata section.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:07 +08:00
Liming Gao b85a6ffb44 UefiCpuPkg CpuDxe: Add nasm source file in CpuDxe.inf
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:06 +08:00
Liming Gao 762e073a93 UefiCpuPkg CpuDxe: Convert Ia32/CpuAsm.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/CpuAsm.asm to Ia32/CpuAsm.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:06 +08:00
Marvin H?user 61257251b2 UefiCpuPkg/SecMain: Decorate phase-transition function with NORETURN.
This patch adds the NORETURN attribute to the function that transfers
to the PEI phase, along with an UNREACHABLE() call at the end to
avoid false warnings.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-06-22 09:37:22 +08:00
Jeff Fan eecad34987 UefiCpuPkg/MtrrLib: Fixed bug if length is less than Fixed-MTRR range
Currently, if the memory length to be programmed is less than the remaining size
of one Fixed-MTRR supported, RETURN_UNSUPPORTED returned. This is not correct.
This is one regression at 07e8892090 when we
updated ProgramFixedMtrr() to remove the loop of calculating Fixed-MTRR Mask.

This fix will calculate Right offset in Fixed-MTRR beside left offset. It
supports small length (less than remaining size supported by Fixed-MTRR) to be
programmed.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-06-07 13:09:25 +08:00
Laszlo Ersek 509f8425b7 UefiCpuPkg: change PcdCpuSmmStackGuard default to TRUE
This Feature PCD causes PiSmmCpuDxe to catch SMM stack overflow at
runtime, logging a clear error message, and entering a CPU dead loop.
Compared to the chaotic and catastrophic consequences of the stack leaking
into, and corrupting, the SMM page table, a stack guard that is enabled by
default is vastly superior.

We should not require sane platforms to explicitly opt in to this
safeguard; instead, we should require platforms that prefer to live
dangerously to opt out of it.

Stack overflow in SMM might even give rise to security vulnerabilities.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/12864
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1341733
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-06-06 10:58:24 +02:00
Jeff Fan 9bedfb2f5b UefiCpuPkg/CpuMpPei: Consume CpuExceptionHandlerLib
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:37:01 +08:00
Jeff Fan a81abf1616 UefiCpuPkg/ExceptionLib: Import PeiCpuExceptionHandlerLib module
This module could be linked by CpuMpPei driver to handle reserved vector list
and provide spin lock for BSP/APs to prevent dump message corrupted.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:36:14 +08:00
Jeff Fan d91225cfad UefiCpuPkg/ExceptionLib: Move global variable location
Move some global variables location from PeiDxeSmmCpuException.c to
DxeCpuException.c and SmmCpuException.c. And remove some un-used global
vairables.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:58 +08:00
Jeff Fan 44ecbc28b6 UefiCpuPkg/ExceptionLib: Add CommonExceptionHandlerWorker()
Add internal worker function RegisterCpuInterruptHandlerWorker().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:53 +08:00
Jeff Fan 670f13af60 UefiCpuPkg/ExceptionLib: Update RegisterCpuInterruptHandlerWorker()
Add parameter CpuExceptionData for RegisterCpuInterruptHandlerWorker().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:48 +08:00
Jeff Fan 9db15f8148 UefiCpuPkg/ExceptionLib: Update UpdateIdtTable()
Add parameter CpuExceptionData for UpdateIdtTable().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:44 +08:00
Jeff Fan ab95e54dc4 UefiCpuPkg/ExceptionLib: Update InitializeCpuExceptionHandlersWorker
Add parameter CpuExceptionData for InitializeCpuExceptionHandlersWorker().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:40 +08:00
Jeff Fan 2c5873fede UefiCpuPkg/ExceptionLib: Add EXCEPTION_HANDLER_DATA definition
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:36 +08:00
Jeff Fan 9b4aa7602e UefiCpuPkg/ExceptionLib: Rename DxeSmmCpuException.c
Rename DxeSmmCpuException.c to PeiDxeSmmCpuException.c that will be used by
PeiCpuExceptionHandlerLib.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:30:38 +08:00
Jeff Fan dc99315b87 UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned buffer
Update MSRs semaphores to the ones in allocated aligned semaphores
buffer. If MSRs semaphores is not enough, allocate one page more.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:22 -07:00
Jeff Fan 695e62d141 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphores
Allocate MSRs semaphores in allocated aligned semaphores buffer.
And add it into semaphores structure.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:17 -07:00
Jeff Fan ed3d5ecb34 UefiCpuPkg/PiSmmCpuDxeSmm: Using CPU semaphores in aligned buffer
Update each CPU semaphores to the ones in allocated aligned
semaphores buffer.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:12 -07:00
Jeff Fan 4e92058113 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for each CPU semaphores
Allocate each CPU semaphores in allocated aligned semaphores buffer.
And add it into semaphores structure.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:07 -07:00
Jeff Fan fe3a75bc41 UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned buffer
Update all global semaphores to the ones in allocated aligned
semaphores buffer.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:01 -07:00
Jeff Fan d67b73cc38 UefiCpuPkg/PiSmmCpuDxeSmm: Move forward MP sync data initialization
Move MP sync data initialization in front of the place that initialize
page table, because the page fault spin lock is allocated in
InitializeMpSyncData() while it is initialized in SmmInitPageTable().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:19:55 -07:00
Jeff Fan 1d64853193 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for global semaphores
Get semaphores alignment/size requirement and allocate aligned
buffer for all global spin lock and semaphores.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:19:47 -07:00
Michael Kinney 728de7a073 UefiCpuPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields check
SMRR range size and alignment should follow the rules like MTRR:
a. The minimum range size is 4 KBytes and the base address of the
   range must be on at least a 4-KByte boundary.
b. For ranges greater than 4 KBytes, each range must be of length
   2^n and its base address must be aligned on a 2^n boundary, where
   n is a value equal to or greater than 12. The base-address
   alignment value cannot be less than its length.
Thus, it could meet "Address_Within_Range AND PhysMask = PhysBase
AND PhysMask".

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2016-05-19 10:04:27 -07:00
Jeff Fan f85d3ce2ef UefiCpuPkg/PiSmmCpuDxeSmm: Use public MSR_IA32_MISC_ENABLE definition
Use the MSR MSR_IA32_MISC_ENABLE definition defined in UefiCpuPkg/Include and
remove the local definition.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16 10:40:19 -07:00
Jeff Fan 846704334c UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Remove unnecessary BTS MSRs
BTS used DS save area by IA32_DS_AREA MSR to get invoker IP instead of the
Last Branch Record Stack. So, removed the unnecessary BTS MSRs.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16 10:40:18 -07:00
Jeff Fan 4b1f9ac19d UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Fix BTS support check bug
SmmProfile feature depends on BTS feature to get the invoker IP (in SMM) from
last branch record. If this feature is not supported, SmmProfile cannot get the
invoker IP (in SMM). Per IA-32 Architectures Software Developer's Manual, BTS
feature is detected by IA32_MISC_ENABLE. If BIT11 of IA32_MISC_ENABLE is set,
BTS is not supported. But current implementation check BIT11 opposite. Also, BTS
feature does not depends on PEBS feature if supported or not.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Shifflett, Joseph <joseph.shifflett@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reported-by: Shifflett, Joseph <joseph.shifflett@hpe.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Shifflett, Joseph <joseph.shifflett@hpe.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16 10:40:16 -07:00
Jeff Fan 07e8892090 UefiCpuPkg/MtrrLib: Remove the loop of calculating Fixed-MTRR Mask
Introduce the 32bit mask seeds to calculate Fixed-MTRR or&and mask values. It
could avoid the loop operation and 64bit shift operations.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29 10:07:07 +08:00
Jeff Fan aaa1e579a5 UefiCpuPkg/MtrrLib: Remove the loop of calculating byte offset in MSR
Calculate byte offset in MSR directly and removing the loop.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29 10:07:06 +08:00
Jeff Fan 0f35412232 UefiCpuPkg/MtrrLib: Reduce the loop time to get fixed-MTRR MSR index
Add input fixed-MTRR MSR index to be start MSR index to avoid finding fixed-MTRR
MSR index from 0 at each time.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29 10:07:06 +08:00
Laszlo Ersek fb8b54694c UefiCpuPkg: CpuIo2Dxe: optimize FIFO reads and writes of IO ports
* Short description:

  The CpuIoServiceRead() and CpuIoServiceWrite() functions transfer data
  between memory and IO ports with individual Io(Read|Write)(8|16|32)
  function calls, each in an appropriately set up loop.

  On the Ia32 and X64 platforms however, FIFO reads and writes can be
  optimized, by coding them in assembly, and delegating the loop to the
  CPU, with the REP prefix.

  On KVM virtualization hosts, this difference has a huge performance
  impact: if the loop is open-coded, then the virtual machine traps to the
  hypervisor on every single UINT8 / UINT16 / UINT32 transfer, whereas
  with the REP prefix, KVM can transfer up to a page of data per VM trap.
  This is especially noticeable with IDE PIO transfers, where all the data
  are squeezed through IO ports.

* Long description:

  The RootBridgeIoIoRW() function in

    PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c

  used to have the exact same IO port acces optimization, dating back
  verbatim to commit 1fd376d9792:

    PcAtChipsetPkg/PciHostBridgeDxe: Improve KVM FIFO I/O read/write
      performance

  OvmfPkg cloned the "PcAtChipsetPkg/PciHostBridgeDxe" driver (for
  unrelated reasons), and inherited the optimization from PcAtChipsetPkg.

  The "PcAtChipsetPkg/PciHostBridgeDxe" driver was ultimately removed in
  commit 111d79db47:

    PcAtChipsetPkg/PciHostBridge: Remove PciHostBridge driver

  and OvmfPkg too was rebased to the new core Pci Host Bridge Driver, in
  commit 4014885ffd:

    OvmfPkg: switch to MdeModulePkg/Bus/Pci/PciHostBridgeDxe

  This caused the optimization to go lost. Namely, the
  RootBridgeIoIoRead() and RootBridgeIoIoWrite() functions in the new core
  Pci Host Bridge Driver delegate IO port accesses to
  EFI_CPU_IO2_PROTOCOL. And, in OvmfPkg (and likely most other Ia32 / X64
  edk2 platforms), this protocol is provided by "UefiCpuPkg/CpuIo2Dxe",
  which lacks the optimization.

  Therefore, this patch ports the C source code logic from commit
  1fd376d979 (see above) to "UefiCpuPkg/CpuIo2Dxe", plus it ports the
  NASM-converted assembly helper functions from OvmfPkg commits
  6026bf4600 and ace1d0517b65:

    OvmfPkg PciHostBridgeDxe: Convert Ia32/IoFifo.asm to NASM

    OvmfPkg PciHostBridgeDxe: Convert X64/IoFifo.asm to NASM

  In order to support the MSFT and INTEL toolchains as well, the *.asm
  files are ported from OvmfPkg as well, immediately from before the above
  conversion (that is, at 6026bf460037^).

* Notes about the port:

  - The write and read branches from commit 1fd376d979 are split to the
    separate functions CpuIoServiceWrite() and CpuIoServiceRead().

  - The EfiPciWidthUintXX constants are replaced with EfiCpuIoWidthUintXX.

  - The cast expression "(UINTN) Address" is replaced with
    "(UINTN)Address" (i.e., no space), because that's how the receiving
    functions spell it as well.

  - The labels in the switch statements are unindented by one level, to
    match the edk2 coding style (and the rest of UefiCpuPkg) better.

* The first signoff belongs to Jordan, because he authored all of
  1fd376d979, 6026bf4600 and ace1d0517b.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://www.redhat.com/archives/vfio-users/2016-April/msg00029.html
Reported-by: Mark <kram321@gmail.com>
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/10424/focus=10432
Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Mark <kram321@gmail.com>
Tested-by: Mark <kram321@gmail.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-04-11 14:11:07 +02:00
Jeff Fan 4da1ebf3b3 UefiCpuPkg/CpuMpPei: Fix potential AP mwait wakeup issue
If ApLoopMode is set to ApInMwaitLoop, AP will be placed into C-State by mwait
instruction. BSP will wakeup AP by write start-up signal in monitor address.
However, AP maybe waken by SMI/NMI/MCE and other condition. On this case, AP
will check if BSP wants to wakeup itself really. If not, AP will continue to
execute mwait to C-State.

One potential issue: BSP may not recognize AP was wakeup from C-State by other
event and BSP still writes start-up signal to wakeup AP. But AP does not aware
it and still execute mwait instruction to C-State. So, AP cannot be wakeup on
this case.

This fix is let AP to clear start-up signal when it really is wakeup to execute
AP function. And BSP will write start-up signal till AP clears it.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-11 14:15:45 +08:00
Jeff Fan f5a2d6f012 UefiCpuPkg/Cpuid.h: Display Intel SGX Resource Enumeration Leaves
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-30 08:29:56 +08:00
Jeff Fan c606a9a5b7 UefiCpuPkg/Cpuid.h: Add CPUID defines and structures for Intel SGX
Add Intel SGX Resource Enumeration Leaves as described by Section 37.7 in
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D,
December 2015.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-30 08:29:49 +08:00
Laszlo Ersek 6c7f3f1d59 UefiCpuPkg: CpuMpPei: remove set but unused variables
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25 10:53:00 +01:00
Laszlo Ersek dc0a714314 UefiCpuPkg: PiSmmCpuDxeSmm: remove set but unused variables
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25 10:52:59 +01:00
Ard Biesheuvel 16e93125b5 UefiCpuPkg/MtrrLib: remove unused but set variable
Remove variable TempQWord that is declared, assigned but never referenced.
This fixes a warning emitted by GCC when -Wunused-but-set-variable is in
effect.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25 10:52:54 +01:00
Michael Kinney 195c94360f UefiCpuPkg/Include: Add top level MSR include file
Add top level MSR include file that includes the Architecural MSR
include file and all family specific MSR files from the Msr
subdirectory

Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 12:00:36 -07:00
Michael Kinney a1e8e34d74 UefiCpuPkg/Include: Add Pentium MSR include file
Add Pentium MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-20.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 12:00:19 -07:00