For instance, in case of CpuHotPlug boot path the platform has already been
initialized. The CPU core should not execute any of the platform initialization
in this case.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13492 6f19259b-4bc3-4df7-8a09-765794883524
Since the System Memory initialization has been moved inside ArmPlatformSecLib
on some platforms, the use of this library could crash if the firmware engineer
forgot to initialize the DRAM.
This library 'patches' the DRAM to add an infinite loop.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13262 6f19259b-4bc3-4df7-8a09-765794883524
The function only used in Secure Firmware used to be mixed with
the Non-Secure/Normal functions in ArmPlatformLib.
When the Secure Firmware was not required for some platforms (eg:
BeagleBoard), these functions were empty functions.
This new interface has been created to clean the ArmPlatformLib
interface between the SEC and PEI phases.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13260 6f19259b-4bc3-4df7-8a09-765794883524
The function 'ArmGicAcknowledgeSgiFrom' was actually acknowledging Interrupts (and not only SGIs).
ArmPkg/ArmGicLib: Introduced the PCD PcdGicPrimaryCoreId
This PCD defines the Id of the primary core in the GIC.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13259 6f19259b-4bc3-4df7-8a09-765794883524
The 'NS' bit must only be set in Secure world to define the Non-Secure region
of the Non-Secure World.
This bit must not be set in Non-Secure World.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13252 6f19259b-4bc3-4df7-8a09-765794883524
Previsouly the synchronization of MpCore was using the SGI (Software
Generated Interrupt) to synchronize MpCore during the early boot.
This commit replaced this mechanism by the more appropriate SEV/WFE
instructions (Send/Wait Event instructions).
That also eases the port to a new cpu/platform.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524
This function was introduced in some drivers to check if the ARM controller
was present in the memory map.
It was using a 8 bit access to get the value from the Identification registers.
These accesses could generate access error on some buses. Instead of replacing
the 8bit access by a 32bit access, these fcuntions have been removed because
they are only useful when the boot firmware is ported on a new platform.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13247 6f19259b-4bc3-4df7-8a09-765794883524
This function returns the address of a Global Variable in the Global Variable Region.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13246 6f19259b-4bc3-4df7-8a09-765794883524
- ArmPlatformNormalInitialize() has been renamed into ArmPlatformInitialize()
- Make the function be called at the early stage of the PEI phase as some
platforms require their interconnects or clocks to be initialize before any
access to Timers or UARTs.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13245 6f19259b-4bc3-4df7-8a09-765794883524
BaseTools now raises an error when a PCD is not declared in a DEC.
This change:
- Remove undeclared PCDs
- Add PCD declaration to DEC file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13195 6f19259b-4bc3-4df7-8a09-765794883524
License.txt is a per-project document showing the license terms
used by that project.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13194 6f19259b-4bc3-4df7-8a09-765794883524
Contributions.txt documents the contribution process for all
tianocore projects. The conents of Contributions.txt should
match in all cases.
License.txt is a per-project document showing the license terms
used by that project.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13187 6f19259b-4bc3-4df7-8a09-765794883524
The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135 6f19259b-4bc3-4df7-8a09-765794883524
This NULL implementation should not affect the existing code flow and
avoid the builds to be broken by a missing dependency.
In a longer term, an implementation of CpuExceptionHandlerLib should
be provided for ARM architecture.
Signed-off-by: oliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13103 6f19259b-4bc3-4df7-8a09-765794883524
Because this driver can be used for different purposes (Terminal, Debug port, communication),
its initialization function has been extended to accept additional settings.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13071 6f19259b-4bc3-4df7-8a09-765794883524
oliviermartin
jljusten