On ARM PLatforms, there is no standard way to know how many cores are
available on the platform.
This PCD is expected to contain this number.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13769 6f19259b-4bc3-4df7-8a09-765794883524
This library could be used before the UEFI phases to expose the CPU state
when an unexpected exception interrupt the firmware.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13767 6f19259b-4bc3-4df7-8a09-765794883524
In case a DebugAgent library is supported for a specific debugger, we would
expect the exception be caught by DebugAgentLib.
The DebugAgentBaseLib exposes the cause of the exception to the user in the
Serial Terminal.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13765 6f19259b-4bc3-4df7-8a09-765794883524
The function only used in Secure Firmware used to be mixed with
the Non-Secure/Normal functions in ArmPlatformLib.
When the Secure Firmware was not required for some platforms (eg:
BeagleBoard), these functions were empty functions.
This new interface has been created to clean the ArmPlatformLib
interface between the SEC and PEI phases.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13260 6f19259b-4bc3-4df7-8a09-765794883524
The 'NS' bit must only be set in Secure world to define the Non-Secure region
of the Non-Secure World.
This bit must not be set in Non-Secure World.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13252 6f19259b-4bc3-4df7-8a09-765794883524
- ArmPlatformNormalInitialize() has been renamed into ArmPlatformInitialize()
- Make the function be called at the early stage of the PEI phase as some
platforms require their interconnects or clocks to be initialize before any
access to Timers or UARTs.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13245 6f19259b-4bc3-4df7-8a09-765794883524
BaseTools now raises an error when a PCD is not declared in a DEC.
This change:
- Remove undeclared PCDs
- Add PCD declaration to DEC file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13195 6f19259b-4bc3-4df7-8a09-765794883524
The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135 6f19259b-4bc3-4df7-8a09-765794883524
This NULL implementation should not affect the existing code flow and
avoid the builds to be broken by a missing dependency.
In a longer term, an implementation of CpuExceptionHandlerLib should
be provided for ARM architecture.
Signed-off-by: oliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13103 6f19259b-4bc3-4df7-8a09-765794883524
CFI Flash differentiates DeviceBaseAddress with BlockAddress in
its protocol. The DeviceBaseAddress was not considered in the
previous version of this driver.
This version also fixes some bugs in the implementation of the
CFI protocol.
This new version also uses the Boot Mode Hob to reinitialized the
FVB when Boot Mode is equal to BOOT_WITH_DEFAULT_SETTINGS.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13064 6f19259b-4bc3-4df7-8a09-765794883524
This library interface is not related to adding extra action to debug support.
But it adds extra action to the ArmPlatform/Sec component.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12861 6f19259b-4bc3-4df7-8a09-765794883524
Memory map remapping is a platform specific feature only enabled by some platforms.
Instead of keeping this function empty for most platforms, the function has been
removed. This feature can easily fit in any other ArmPlatformLib function.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12632 6f19259b-4bc3-4df7-8a09-765794883524
This change does not make possible to disable Trustzone from the firmware.
The firmware has to be built for Trustzone support enabled or disabled.
The memory page table are now defined as 'Normal Memory' in any case.
Except for RTSM Device Memory which as to be Secure Device Memory due
to a RTSM bug.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12452 6f19259b-4bc3-4df7-8a09-765794883524
Every CPUs have their own initialization requirements.
This library allows to allows to abstract these initialization requirements
into the ARM Platform common components.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12448 6f19259b-4bc3-4df7-8a09-765794883524
The denomination 'Normal' was used to make reference to the 'Normal'
or 'Non Secure' or 'Non Trusted' world.
To avoid confusion, this prefix has been removed from PCDs to define
the normal world.
The PCDs explicitely related to the Secure/Trusted World continue to
have the 'Sec' prefix.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12416 6f19259b-4bc3-4df7-8a09-765794883524
In the previous version, every cores had the same stack size.
To avoid to waste memory with secondary core stacks, the primary core stack
size is now different from the secondary cores stack size.
These are the Stack PCDs and their default values:
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12415 6f19259b-4bc3-4df7-8a09-765794883524
On MpCore system, the primary core can now be any core of the system.
To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask'
and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'.
These PCDs by default use the ClusterId and CoreId to identify the core. And the
primary core is defined as the ClusetrId=0 and CoreId=0.
The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId),
GET_CORE_POS(MpId), PRIMARY_CORE_ID.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412 6f19259b-4bc3-4df7-8a09-765794883524
This library is the interface for the ARM Generic Interrupt Controller
Architecture Specification.
ARM Platform can use any GIC controller (not necessary PL390 GIC).
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12411 6f19259b-4bc3-4df7-8a09-765794883524
This library that uses the DebugAgentLib interface prints the loaded addresses
of the SEC and PEI_CORE module using PeCoffExtraActionLib.
Note: Because there is no PE loader for these XIP modules, PeCoffExtraActionLib is not invoked.
This library scans the firmware volume to find these modules and calculate their fixup loaded
addresses used to load their symbols in the debugger.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12023 6f19259b-4bc3-4df7-8a09-765794883524
In the former memory model, the UEFI firmware was expected to be located
at the top of the system memory. Stacks & Pi memory regions were set below
the firmware.
On some platform, the UEFI firmware could be shadowed by the ROM firmware
(case of the BeagleBoard) and in some cases the firmware is copied at the
beginning of the system memory.
With this new memory model, stack and Pi/DXE memory regions are set at the
top of the system memory wherever the UEFI firmware is located in the memory
map.
Because DXE core does not support shadowed firmwares, the system memory covered
by the UEFI firmware is marked as 'Non Present' to avoid to be overlapped by
DXE allocations.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11992 6f19259b-4bc3-4df7-8a09-765794883524
oliviermartin