AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a
AND with the immediate inverted, but Clang's integrated assembler emits an
error.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
The AARCH64 LDR and STR instructions only support signed offsets for post- and
pre-indexed addressing. For normal signed offset addressing, the mnemonic is
STUR. GNU As automatically assembles STR with signed offset as STUR, but Clang's
integrated assembler doesn't.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15508 6f19259b-4bc3-4df7-8a09-765794883524
GNU as assembles instructions without the '#' before immediates. Clang doesn't.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15507 6f19259b-4bc3-4df7-8a09-765794883524
This ensures the .type directive is used to mark them as function symbols
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
Some non-GCC toolchain might support the GNU assembly language.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brendan Jackman <brendan.jackman@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
Current EDK2 source code does actually trigger nested interrupted (even if
the PI spec says interrupt should not be nested).
This issue has highlighted the lack of restoring ELR_EL2/ELR_EL1 register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off: Vijayakumar Subbu <vsubbu@nvidia.com>
Signed-off: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15481 6f19259b-4bc3-4df7-8a09-765794883524
The function was allocating a buffer for the read value from the UEFI Variable.
But it was returning the pointer of the default value when the variable was
not present.
It could cause error when the default value and the returned value were free
when these addresses were the same (double FreePool on the same address).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15427 6f19259b-4bc3-4df7-8a09-765794883524
There are several instances of asserts which do not also handle
the error condition in Release builds.
Because these functions are called in different location of the
code and their parameters might change during the execution, it
is safer to handle the error.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15399 6f19259b-4bc3-4df7-8a09-765794883524
On CortexA5x the SMP bit is BIT6 of CPUECTLR_EL1 register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15398 6f19259b-4bc3-4df7-8a09-765794883524
This register is A5x specific. It is the reason why the code moved from ArmLib
to ArmCpuLib/ArmCortexA5xLib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
PartNum is the field of MIDR that returns the CPU name.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15395 6f19259b-4bc3-4df7-8a09-765794883524
The arguments passed to the semi-hosing backend should
be of 'native' size to match register widths.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15389 6f19259b-4bc3-4df7-8a09-765794883524
CTR (Cache Type Register) has the same format on ARMv7 and AArch64.
Renaming Cp15CacheInfo() into ArmCacheInfo() makes this function
architecture independent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15381 6f19259b-4bc3-4df7-8a09-765794883524
The function ArmReadMidr has been recently added, but that functionality was
already present under other names such as Cp15IdCode and ArmMainIdCode. This
change removes redundant code and moves the function to the Common library.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276 6f19259b-4bc3-4df7-8a09-765794883524
A warning is reported because ArmArchTimerReadReg may theoretically result
in an unititialised value.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15275 6f19259b-4bc3-4df7-8a09-765794883524
Several assembler macros use a loop at the label "dead" to trap an error.
This is difficult to debug as there is no indication of how one arrived at the loop.
This change replaces dead with distinct loops locally in the macro,
which means the cause of the hang is detectable to the debugger.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15273 6f19259b-4bc3-4df7-8a09-765794883524
MachineType was used on 32-bit.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15239 6f19259b-4bc3-4df7-8a09-765794883524
This header contains a function that does not exist.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15238 6f19259b-4bc3-4df7-8a09-765794883524
The function ArmWriteVBar had a UINT32 parameter.
Need to change it to UINT.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15208 6f19259b-4bc3-4df7-8a09-765794883524
Update the LastBlockEntry return value when allocating a new page table block
and the parent page table entry is not valid. Discovered when producing page
table entries for a memory region that spans multiple page table entries of a
parent page table block. Not very memory space efficient because the rest of
the code could calculate a required page level that is deeper than some blocks
of the memory region might require. Case that found the problem:
MemoryRegion->VirtualBase = 0
MemoryRegion->Length = 0x7F000000
This fix will create an un-needed level of page table for address
range 0 -> 0x40000000
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15177 6f19259b-4bc3-4df7-8a09-765794883524
This code also removed some redundant instructions.
__aeabi_memcpy doesn't require preservation of r0 (as memcpy does),
which could save a push, but the code has been left to keep things consistent.
The reason __aeabi_memcpy has been added to the .S file is so it will be available
to toolchains that use the GCC assembler but the full ARM EABI (i.e. current LLVM)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15124 6f19259b-4bc3-4df7-8a09-765794883524
The System Memory region might be out of the 32-bit memory space.
This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:
- # System Memory (2GB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
EFI Shell and Linux kernel boot successfully.
Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
'inline' keyword is not supported by the C89 (version used by EDK2).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14957 6f19259b-4bc3-4df7-8a09-765794883524
When the Device Tree was loaded above the 32bit address space the operation:
*RelocatedFdt = ALIGN ((UINT64)*RelocatedFdt, (UINT32)FdtAlignment);
was returning an incorrect address.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14915 6f19259b-4bc3-4df7-8a09-765794883524
When loaded above the 32-bit address space the address requires more than 8 characters.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14913 6f19259b-4bc3-4df7-8a09-765794883524
The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC).
Note: SVC might be generated by debuggers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
These functions are not chipset specific.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
The aim is to make this driver follows the ARM GIC specifications and
be implementation independent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero).
So the previous assertion was not correct.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
TT_ADDRESS_* macros were not casting immediate values to UINTN.
This causes shift operations to be off by 32-bits when calculating
addresses above 4GB. Any address above 4GB was being improperly calculated.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14777 6f19259b-4bc3-4df7-8a09-765794883524
Table Descriptor and Level-3 Block entry descriptors have the same
translation table type value (ie: 0x3).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
The shift by 1 on the left was expected. It eases the access to CSSELR and set/way operations
where the cache level field is at the BIT1 position.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14704 6f19259b-4bc3-4df7-8a09-765794883524
The wrong attribute was used to set the region.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
The exception handling support code appears to adjust the stack pointer in the wrong direction.
It decrements the stack pointer by 0x60, but this should be an increment (add) for the
downward-growing stack.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
The ConfigureMmu() function is unused - the only call to it
is commented out, and the functionality has been moved to
InitMmu() in MemoryInitPeiLib.c.
This change also removes the unused definitions from the file.
Change-Id: Ice795bfee25c403142d0c078533f8a46d04f82e9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Signed-off-by:: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14621 6f19259b-4bc3-4df7-8a09-765794883524
These macros are helper functions to get the information from the GIC CPU
Interface Identification register.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14582 6f19259b-4bc3-4df7-8a09-765794883524
This is already taken care by Sec when PcdTrustzoneSupport = TRUE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
Changing the attribute implies some cache management (clean & invalidate).
Preventing the cache management should improve the performance.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
This helper function converts the section attributes into their page equivalents.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
This macro return the address of the last entry of a translation table.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
- Fix the length used to set the GCD Memory Space attribute
- Print a warning message if the given length of a memory space region is not 4KB-aligned
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
During the interrupt registration comparison is made against
max value of exception types for ARMV7, but in the common handling
function the check is made against max value of exceptions types
for ARMV8. This can lead to undefined behaviour during registration
of interrupts.
This patch modifies the registration function to handle only AArch64
exceptions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Girish K S <ks.giri@samsung.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only
be invoked from EL2.
The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates
the TLBs of the current VMID.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
Some missing files from the initial AArch64 commit.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14488 6f19259b-4bc3-4df7-8a09-765794883524
The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first
registers of the GIC CPU Target Registers.
The first GIC Distributor Target registers correspond to the SGIs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
Route both the setting and restoring of cacheability through DXE Services/GCD
and stop using the CPU AP directly.
The patch also removes all references to the CPU AP which eliminates the need
for a library constructor.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Senthil Ramakrishnan <senthil.ramakrishnan@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14468 6f19259b-4bc3-4df7-8a09-765794883524
The UEFI specification mandates that software uses the DescriptorSize returned
by the GetMemoryMap() function to find the start of each EFI_MEMORY_DESCRIPTOR
in the MemoryMap array. This allows for future expansion of the EFI_MEMORY_DESCRIPTOR.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14447 6f19259b-4bc3-4df7-8a09-765794883524
ATAG is specific to 32bit ARM architecture.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14435 6f19259b-4bc3-4df7-8a09-765794883524
- Registering a interrupt handler implicitly enables said interrupt. This
is in the UEFI Spec. No need to enable the interrupts a second time.
- Make sure the Timer is completely disabled before configuring it. Only
enable after configuration is complete.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14433 6f19259b-4bc3-4df7-8a09-765794883524
* Fix name of 'device_type' and 'migrate' properties.
* Fix 'reg' property. It is supposed to contain the CPU MPIDR of the
CPU being described.
* Fix byte ordering of data in 'psci' node.
* Fix some problems regarding the size of data. In a number of places
it was assumed data would be 32-bits wide.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14351 6f19259b-4bc3-4df7-8a09-765794883524
Introduce cpu_to_fdtn() function which will call the appropriate 32-bit
or 64-bit version based on the size of a native integer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14350 6f19259b-4bc3-4df7-8a09-765794883524
PrepareFdt() function was getting pretty fat and big functions are more
complex to understand and find the information one is looking for.
This patch extracts some code from PrepareFdt() function and put it
in some new functions.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14349 6f19259b-4bc3-4df7-8a09-765794883524
Checking if a core if the primary/boot core used to be done with the macro
IS_PRIMARY_CORE().
Some platforms exposes configuration registers to change the primary core.
Replacing the macro IS_PRIMARY_CORE() by ArmPlatformIsPrimaryCore() allows
some flexibility in the way to check the primary core.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14344 6f19259b-4bc3-4df7-8a09-765794883524
PcdArmLinuxKernelFixedOffset is supposed to indicate the offset from
the beginning of the system memory at which the kernel will be loaded.
However, this PCD value is not used at all. Instead the kernel is loaded
just below a certain limit indicated by PCD value PcdArmLinuxKernelMaxOffset.
This patch deletes PCD value PcdArmLinuxKernelFixedOffset to avoid any
confusion.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14273 6f19259b-4bc3-4df7-8a09-765794883524
This patch corrects a problem detecting uInitrd signature when booting
with FDT.
BdsBootLinuxFdt was attempting to read the signature from InitrdImage which
is zero at this point in the code. The code now reads the signature from
InitrdImageBase.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14272 6f19259b-4bc3-4df7-8a09-765794883524
UEFI must not add additional 'cpu' nodes if the 'cpus' node was already present.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14271 6f19259b-4bc3-4df7-8a09-765794883524
"ARMH" is the Four-Letter unique identifier used by ARM in the context
of the fast SMC identification interface.
This patch properly defines this value in a header file instead
of using the numeric value directly in the code.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14268 6f19259b-4bc3-4df7-8a09-765794883524
If we have a pending spurious interrupt we should not try to clear it,
just ignore.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14265 6f19259b-4bc3-4df7-8a09-765794883524
- An Ascii filename must be passed to the TFTP service (was a Unicode filename)
- If the PXE service had already configured the connection we need to restart
when we want to download a new file or do a do a PXE Boot.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14195 6f19259b-4bc3-4df7-8a09-765794883524
Not freeing the memory prevents Linux to be started again.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14193 6f19259b-4bc3-4df7-8a09-765794883524
Add some checks in the code loading an FDT blob from a memory-mapped device
so that UEFI will detect and print an error message if the address
range doesn't cover the whole file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14192 6f19259b-4bc3-4df7-8a09-765794883524
EFI Shell adds '\\' in front of the filename.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14188 6f19259b-4bc3-4df7-8a09-765794883524
The comment says we cannot list files in the Semihosting FileSystem.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14187 6f19259b-4bc3-4df7-8a09-765794883524
Go through the UEFI memory map and add OS 'runtime' regions as
reserved regions to the Device Tree.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14183 6f19259b-4bc3-4df7-8a09-765794883524
Rename GetEnvironmentVariable() function into GetGlobalEnvironmentVariable().
GetEnvironmentVariable() function sill exists but caller must now pass a Guid.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14176 6f19259b-4bc3-4df7-8a09-765794883524
A ArmSmcLib Null implementation has also been added for CPU without the ARM Security
Extension (Trustzone support).
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14164 6f19259b-4bc3-4df7-8a09-765794883524
This check prevents to get an assertion in case of null PdbPointer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14163 6f19259b-4bc3-4df7-8a09-765794883524
This constant allows to reduce architecture difference in the position
of the IRQ in the exception table.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14099 6f19259b-4bc3-4df7-8a09-765794883524
Add '.' to the list of directories recognised as the root directory
of semi-hosting.
This is important for EdkShell because listing files in the root directory
of semi-hosting (e.g. ls fsnt0:) is tranformed in a way that uses '.'
Without this patch this results in EdkShell hanging and returning
an "Out of resources" error in the end. With this patch the command
is immediately recognised as unsupported.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14089 6f19259b-4bc3-4df7-8a09-765794883524
The new functions are:
- ArmPlatformStackSet(IN UINTN StackBase, IN UINTN MpId, IN UINTN PrimaryStackSize, IN UINTN SecondaryStackSize);
- ArmPlatformStackSetPrimary(IN UINTN StackBase, IN UINTN MpId, IN UINTN PrimaryStackSize, IN UINTN SecondaryStackSize);
- ArmPlatformStackSetSecondary(IN UINTN StackBase, IN UINTN MpId, IN UINTN PrimaryStackSize, IN UINTN SecondaryStackSize);
The stack topology can be changed by implementing a new ArmPlatformStackLib
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13774 6f19259b-4bc3-4df7-8a09-765794883524
This library could be used before the UEFI phases to expose the CPU state
when an unexpected exception interrupt the firmware.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13767 6f19259b-4bc3-4df7-8a09-765794883524
In case a DebugAgent library is supported for a specific debugger, we would
expect the exception be caught by DebugAgentLib.
The DebugAgentBaseLib exposes the cause of the exception to the user in the
Serial Terminal.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13765 6f19259b-4bc3-4df7-8a09-765794883524
Use the library libdt from the Device Tree Compiler project.
The used version is from Wednesday 22nd August 2012 (commit: 8716901d2215a3)
The Device Tree Compiler project is under dual BSD/GPL license (it means the
license is either BSD or GPL). The BSD license is the license that fits to the
Tianocore contribution requirements.
The use of libfdt into Tianocore has been authorised by David Gibson the
author of libfdt and its current maintainer Jon Loeliger (email thread on 7th
September 2011).
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13760 6f19259b-4bc3-4df7-8a09-765794883524
EFI_MEMORY_UC is mapped to Strongly Ordered memory while EFI_MEMORY_WC is
mapped to Uncached Normal/System memory.
This change improve performance while accessing uncached regions in the
System Memory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Olivier Martin <oliviermartin@arm.com
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13693 6f19259b-4bc3-4df7-8a09-765794883524
Because the D&I caches were clean before to be disabled, the cache
lines might have got dirty during the cache maintenance operations.
This fix disables D&I caches before to clean them. The performance
drops should be minimised as invalidating the I cache is only a
couple of instruction.
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13503 6f19259b-4bc3-4df7-8a09-765794883524
If the first call of gBS->GetMemoryMap() succeeded (could happen if the Memory Map
has changed between the two gBS->GetMemoryMap() calls) in the loop block then
gBS->ExitBootServices() was never called.
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13500 6f19259b-4bc3-4df7-8a09-765794883524
The function 'ArmGicAcknowledgeSgiFrom' was actually acknowledging Interrupts (and not only SGIs).
ArmPkg/ArmGicLib: Introduced the PCD PcdGicPrimaryCoreId
This PCD defines the Id of the primary core in the GIC.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13259 6f19259b-4bc3-4df7-8a09-765794883524
The 'NS' bit must only be set in Secure world to define the Non-Secure region
of the Non-Secure World.
This bit must not be set in Non-Secure World.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13252 6f19259b-4bc3-4df7-8a09-765794883524
Previsouly the synchronization of MpCore was using the SGI (Software
Generated Interrupt) to synchronize MpCore during the early boot.
This commit replaced this mechanism by the more appropriate SEV/WFE
instructions (Send/Wait Event instructions).
That also eases the port to a new cpu/platform.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524
License.txt is a per-project document showing the license terms
used by that project.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13194 6f19259b-4bc3-4df7-8a09-765794883524
Contributions.txt documents the contribution process for all
tianocore projects. The conents of Contributions.txt should
match in all cases.
License.txt is a per-project document showing the license terms
used by that project.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13187 6f19259b-4bc3-4df7-8a09-765794883524
The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135 6f19259b-4bc3-4df7-8a09-765794883524
ArmEnableVFP could crash on an out-of-order CPU. Adding an instruction barrier after writing to CPACR cures the problem.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13134 6f19259b-4bc3-4df7-8a09-765794883524
Some ARM Platform components (ie: PrePei) use this constructor name to
initialize the timers (at this time there is no PE loader to call the
library constructors) when PI/UEFI is started to initialize the
PerformanceLib.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13041 6f19259b-4bc3-4df7-8a09-765794883524
This patch adds support to invalidate Instruction Cache to the Point of Unification (PoU).
Signed-off-by: eugenecohen
Reviewed-by: oliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13012 6f19259b-4bc3-4df7-8a09-765794883524
Changed ARM CPU SetMemoryAttributes to always use strongly ordered for the EFI_MEMORY_UC attribute.
Signed-off-by:
Reviewed-by: eugenecohen
Reviewed-by: yanivtal
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13011 6f19259b-4bc3-4df7-8a09-765794883524
The initrd was loaded at the top of the UEFI System Memory. By consequence, if the system memory
was reduced by the Linux command line then the initrd was not part of the system memory.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12994 6f19259b-4bc3-4df7-8a09-765794883524
Change __aeabi_uread4 from:
ldrb r2, [r0, #1]
ldrb r1, [r0]
(...)
to:
ldrb r1, [r0]
ldrb r2, [r0, #1]
(...)
This change is a workaround to handle correctly __aeabi_uread4 on ARM
Versatile Express RTSM.
It should not have any major consequence on the other ARM platforms.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12481 6f19259b-4bc3-4df7-8a09-765794883524
This change does not make possible to disable Trustzone from the firmware.
The firmware has to be built for Trustzone support enabled or disabled.
The memory page table are now defined as 'Normal Memory' in any case.
Except for RTSM Device Memory which as to be Secure Device Memory due
to a RTSM bug.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12452 6f19259b-4bc3-4df7-8a09-765794883524
Every CPUs have their own initialization requirements.
This library allows to allows to abstract these initialization requirements
into the ARM Platform common components.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12448 6f19259b-4bc3-4df7-8a09-765794883524
This library hides where the 'XIP' Global Variable are located in the memory.
It is expected the Sec/PrePi modules define the Global Variable area through
the GlobalVariable HOB.
The ArmPlatformGlobalVariableLib library allows access to global variables by
their offsets in this region.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12420 6f19259b-4bc3-4df7-8a09-765794883524
The denomination 'Normal' was used to make reference to the 'Normal'
or 'Non Secure' or 'Non Trusted' world.
To avoid confusion, this prefix has been removed from PCDs to define
the normal world.
The PCDs explicitely related to the Secure/Trusted World continue to
have the 'Sec' prefix.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12416 6f19259b-4bc3-4df7-8a09-765794883524
In the previous version, every cores had the same stack size.
To avoid to waste memory with secondary core stacks, the primary core stack
size is now different from the secondary cores stack size.
These are the Stack PCDs and their default values:
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12415 6f19259b-4bc3-4df7-8a09-765794883524
On MpCore system, the primary core can now be any core of the system.
To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask'
and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'.
These PCDs by default use the ClusterId and CoreId to identify the core. And the
primary core is defined as the ClusetrId=0 and CoreId=0.
The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId),
GET_CORE_POS(MpId), PRIMARY_CORE_ID.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412 6f19259b-4bc3-4df7-8a09-765794883524
This library is the interface for the ARM Generic Interrupt Controller
Architecture Specification.
ARM Platform can use any GIC controller (not necessary PL390 GIC).
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12411 6f19259b-4bc3-4df7-8a09-765794883524
There are two variants of the Linux Loader EFI application:
- the ATAG version 'LinuxAtagLoader.inf': expect to start an ATAG 'zImage'
in the same directory as the EFI application
- the FDT version 'LinuxFdtLoader.inf': load the FDT blob 'platform.dtb'
and the FDT 'zImage' from the same directory as the EFI application.
When these applications are started without any argument, a menu appears
to the user to create/update a boot entry.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12410 6f19259b-4bc3-4df7-8a09-765794883524
Separate the BdsBootLinux() function into two functions for Atag and Fdt specific Linux booting
- BdsBootLinuxAtag ()
- BdsBootLinuxFdt ()
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12408 6f19259b-4bc3-4df7-8a09-765794883524
Missing from my commit "ArmPkg/BdsLib: Move some functions used to
create/update BDS Boot Entry from ArmPlatformPkg/Bds to
ArmPkg/BdsLib"
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12325 6f19259b-4bc3-4df7-8a09-765794883524
The previous version was only checking if the Remaining Device Path node
was a MemMap DevicePath node.
This fix also checks if the Root DevicePath node is a MemMap DevicePath node.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12315 6f19259b-4bc3-4df7-8a09-765794883524
This structure is defined by the UEFI specification and has a better location in BdsLib.
ArmPlatformPkg/Bds: Encapsulate the BDS_LOAD_OPTION into a list entry structure
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12312 6f19259b-4bc3-4df7-8a09-765794883524
Some coherencies issues were existing in the former version of DmaLib.
These issues could have for consequences to not make the MdeModulePkg/Bus/Usb
software stack not work.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12137 6f19259b-4bc3-4df7-8a09-765794883524
This library is used to display the loaded address of the 'Sec' at the early
stage of the boot process. The debug command line generated by PeCoffExtraActionLib
can be used for Source Level Debugging at the early stage of the UEFI boot process.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12136 6f19259b-4bc3-4df7-8a09-765794883524
Brendan Jackman
Olivier Martin
oliviermartin
Harry Liebel
Garrett Kirkendall
Leif Lindholm
Eugene Cohen
Roy Franz
Girish K S
oliviermartin
jljusten