Commit Graph

1027 Commits

Author SHA1 Message Date
Jeff Fan b8caae191c UefiCpuPkg/PiSmmCpuDxeSmm: Consume new APIs
Consuming PeCoffSerachImageBase() from PeCoffGetEntrypointLib and consuming
DumpCpuContext() from CpuExceptionHandlerLib to replace its own implementation.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-04-07 09:43:48 +08:00
Jeff Fan 1b2f7b3e49 UefiCpuPkg/CpuExceptionHandlerLib: Add DumpCpuContext() implementation
Export DumpCpuCotext() to display CPU Context. We will invoke
PeCoffGetEntrypointLib's PeCoffSerachImageBase() to get PE/COFF image base.
Display exception data bit value for page fault exception.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-04-07 09:43:44 +08:00
Jeff Fan cb811673c7 UefiCpuPkg/MpLib.c: Load microcode before mtrr sync per IA32 SDM
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=453
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-04-06 16:06:25 +08:00
Dandan Bi 245e98bfcb UefiCpuPkg: Fix typos in UefiCpuPkg.dec
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-04-06 09:02:36 +08:00
Jeff Fan 80c4b23638 UefiCpuPkg/CpuFeatures: Change files format to DOS
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-04-05 16:33:16 +08:00
Dandan Bi 3ff1e8987b UefiCpuPkg/MtrrLib:Fix VS2012 build failure
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2017-04-05 11:26:55 +08:00
Jeff Fan ee58438970 UefiCpuPkg/PiSmmCpuDxeSmm: Update saved SMM ranges check in SmmProfile
SmmProfile feature required to protect all SMM ranges by structure
mProtectionMemRangeTemplate. This update is to add additonal save SMM ranges
into mProtectionMemRangeTemplate besides the range specified by
mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-04-01 11:45:00 +08:00
Jeff Fan 97f1061e8b UefiCpuPkg/PiSmmCpuDxeSmm: Add IsInSmmRanges() to check SMM range
Internal function IsInSmmRanges() is added t check SMM range by saved SMM ranges
beside by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-04-01 11:44:55 +08:00
Jeff Fan 7ed6f78145 UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables
v2:
  Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-04-01 11:44:44 +08:00
Ruiyu Ni 4ef6c3850e UefiCpuPkg/MtrrLib: Fix GCC build failure
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
2017-03-31 22:05:21 +08:00
Ruiyu Ni af8388059a UefiCpuPkg/MtrrLib: All functions use definitions in Msr.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:35 +08:00
Ruiyu Ni 10c361ad02 UefiCpuPkg/MtrrLib: Refine MtrrGetMemoryAttributeByAddressWorker
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:34 +08:00
Ruiyu Ni 8051302a36 UefiCpuPkg/MtrrLib: Use a better algorithm to calculate MTRR
The new algorithm finds out the more optimal MTRR solution for
current memory type settings.
Compare against the original algorithm, the new one guarantees
to find the correct MTRR solution, but doesn't guarantee to
find the most optimal MTRR solution.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:33 +08:00
Ruiyu Ni 012f4054db UefiCpuPkg/MtrrLib: MtrrLibInitializeMtrrMask() uses definitions in CpuId.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:33 +08:00
Ruiyu Ni b8f015999e UefiCpuPkg/MtrrLib: Add MtrrLib prefix to several internal functions
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:32 +08:00
Ruiyu Ni 94240f1b05 UefiCpuPkg/MtrrLib: Add MtrrLib prefix to ProgramFixedMtrr
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:32 +08:00
Ruiyu Ni 386f5785ea UefiCpuPkg/MtrrLib: GetVariableMtrrCountWorker uses definitions in Msr.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:31 +08:00
Ruiyu Ni 3bb13d35d6 UefiCpuPkg/MtrrLib: IsMtrrSupported uses definitions in Msr.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:31 +08:00
Ruiyu Ni 78c4992529 UefiCpuPkg/MtrrLib: Add CacheInvalid enum type to MtrrLib.h
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:30 +08:00
Ruiyu Ni 341fea6438 UefiCpuPkg/MtrrLib: Correct typo in comments and remove TABs
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-31 13:57:30 +08:00
Jeff Fan 844b2d072d UefiCpuPkg/MpLib.c: Add checking CR0 PG bit
If CR0 PG bit is not set, it means paging is not enabled on BSP. Thus, Execute
Disable feature is not working actually. Thus, we cannot enable it on APs.

v2:
  Correct the commit log.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-28 09:49:29 +08:00
Jeff Fan 98eb009563 UefiCpuPkg: Add new PCDs PROMPT/HELP string in UNI file
Correct PCD declaration comments and add new PCDs in UNI file.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-28 09:00:15 +08:00
Jeff Fan 22223480bf UefiCpuPkg/CpuCommonFeaturesLib: Generate new INF GUID value
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-28 09:00:07 +08:00
Jeff Fan 94dddca718 UefiCpuPkg/RegisterCpuFeaturesLib: Fix meta data comments
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-28 09:00:02 +08:00
Jeff Fan 9a5f0e908d UefiCpuPkg/RegisterCpuFeaturesLib: Remove static type
Using one specific name for global variable to save MP services protocol
pointer.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-28 08:59:58 +08:00
Jeff Fan 8d5df9d78f UefiCpuPkg/RegisterCpuFeaturesLib: Fix the function header issues
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-28 08:59:53 +08:00
Jeff Fan 0b36d8fa73 UefiCpuPkg/RegisterCpuFeaturesLib: Add ASSERT on allocated memory
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-27 16:18:09 +08:00
Jeff Fan 30b7a50bac UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address
The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to
indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type
actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB.

This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field
HighIndex to indicate the high 32bit MMIO address and original Index still
indicate the low 32bit MMIO address.

This update makes use of original padding space between ValidBitLength and
Value to add HighIndex.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-27 16:18:04 +08:00
Jeff Fan 98387f54ae UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64
The input parameter Index of PreSmmCpuRegisterTableWrite() and
CpuRegisterTableWrite() is defined as UINT32. Index is MSR/MMIO address that
will be saved in CPU register table. UINT32 blocks the MMIO address > 4GB.

This fix is to define Index to UINT64 instead of UINT32.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-27 16:18:00 +08:00
Jeff Fan cab6b79cf4 UefiCpuPkg/RegisterCpuFeaturesLib: Set CpuFeatureEntry initial value
CpuFeatureEntry will be set before using it. But VS2012 build reported the build
warning "potentially uninitialized local variable 'CpuFeatureEntry' used".

This fix is to set CpuFeatureEntry initial value and add ASSERT check later.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-23 10:00:53 +08:00
Jeff Fan afc6201759 UefiCpuPkg/CpuCommonFeaturesLib: Fix case write issue
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-23 09:19:26 +08:00
Jeff Fan 82e75ac65a UefiCpuPkg: Add CPU Features PEI/DXE drivers
They will consume Register CPU Features library to detect and initialize CPU
features.

CpuFeaturesPei driver is used to initialize CPU features in PEI phase.
CpuFeaturesDxe driver is used to initialize CPU features in DXE phase.

Add PcdCpuFeaturesInitAfterSmmRelocation and PcdCpuFeaturesInitOnS3Resume
that consumed by CpuFeaturesPei and CpuFeaturesDxe.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:12:02 +08:00
Jeff Fan 0a70d1c304 UefiCpuPkg: Add NULL CPU Common Features Library instance
This NULL CPU common Features Library instance will register some CPU features
defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR).

Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL
CPU Common Features Library instance.

v2:
  1. Using MSR_IA32_EFER to enable/disable NX feature instead of using
     MSR_IA32_MISC_ENABLE.
  2. Fix bug that SMX and VMX feature is swapped.

v3:
  1. Add AesniGetConfigData() to get current register state.

v5:
  Move MSR reading from AesniGetConfigData() to AesniSupport().

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:58 +08:00
Jeff Fan eff78ac35b UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances
PEI Register CPU Features Library instance is used to register/manager/program
CPU features on PEI phase.
DXE Register CPU Features Library instance is used to register/manager/program
CPU features on DXE phase.

v2:
  Format debug messages.

v3:
  Trim white space at end of line.

v4:
  Remove unused local variable.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:53 +08:00
Jeff Fan 548013c07f UefiCpuPkg/Include/Library: Add Register CPU Features Library
Register CPU Features Library is used to register/manage/program CPU features.
NULL CPU features library instance could consume it register CPU features
functions.
CPU Feature module could consume this library to detect/analysis/program CPU
features on BSP/APs.

v4:
  Fix GCC build issue.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:49 +08:00
Jeff Fan e000e774cd UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid
GUID gEdkiiCpuFeaturesInitDoneGuid is used to indicate if CPU features have been
initialized.

On PEI phase, one gEdkiiCpuFeaturesInitDoneGuid PPI will be installed after CPU
features initialized.
On DXE phase, one gEdkiiCpuFeaturesInitDoneGuid Protocol will be installed after
CPU features initialized.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:45 +08:00
Jeff Fan 98f4a5653d UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid
GUID gEdkiiCpuFeaturesSetDoneGuid is used to indicate if CPU feature related
setting are set finished. For example, PCD PcdCpuFeaturesUserConfiguration.

On PEI phase, one gEdkiiCpuFeaturesSetDoneGuid PPI will be installed after
platform set CPU feature setting.
On DXE phase, one gEdkiiCpuFeaturesSetDoneGuid Protocol will be installed after
platform set CPU feature setting.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:41 +08:00
Jeff Fan 7eee4e1e3c UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs
PcdCpuFeaturesSupport supports PcdsFixedAtBuild/PcdsPatchableInModule types and
used to add/remove CPU feature from firmware during build time.

PcdCpuFeaturesUserConfiguration supports all PCD types and used to configurate
CPU features by platforms.

PcdCpuFeaturesCapability supports PcdsDynamic PCD and used to indicate the CPU
features capability on processors.

PcdCpuFeaturesSetting supports PcdsDynamic PCD and used to indicate the current
CPU features setting on processors.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:38 +08:00
Jeff Fan f4c982bf09 UefiCpuPkg/Msr: Add CPUID signature check MACROs
All model-specific MSRs are related to processor signatures that are defined in
each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:34 +08:00
Jeff Fan 30d995ee08 UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Needn't to copy register table if AllocatedSize is 0.

v4:
  Fix potential uninitialized variable issue.

v5:
  Set DestinationRegisterTableList[Index].RegisterTableEntry before
  RegisterTableEntry is updated.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:29 +08:00
Jeff Fan 8b371e93f2 UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress
If PCD PcdCpuS3DataAddress is set before, CpuS3DataDxe should get RegisterTable
and PreSmmRegisterTable from existing PCD pointed buffer and needn't to allocate
new buffer for RegisterTable and PreSmmRegisterTable.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:25 +08:00
Jeff Fan 9cc45009ba UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type
Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to
CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit
PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry.

This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and
make RegisterTableEntry is fixed length.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22 10:11:21 +08:00
Jeff Fan 01eb3f39bb UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check
The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors.
Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is
supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0).

Cc: Anthony PERARD <anthony.perard@citrix.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-17 13:55:12 +08:00
Hao Wu e62a0eb61b UefiCpuPkg/PiSmmCpuDxeSmm: Refine casting result to bigger size
The commit is a follow-up of commit 8491e30.

In file MpService.c line 786:
Pte[Index] = (UINT64)((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) |
mAddressEncMask ...

(Where PageTable is of type VOID*, Index is of type UINTN, mAddressEncMask
is of type UINT64 and Pte[Index] is of type UINT64.)

Since in this case, the code logic ensures that the expression will not
exceed the range of UINTN, the commit will remove the explicit type cast
'(UINT64)'.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-08 08:59:21 +08:00
Leo Duran 627dcba352 UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables entries are created or modified.

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-06 15:34:24 +08:00
Hao Wu 8491e302e1 UefiCpuPkg: Refine casting expression result to bigger size
There are cases that the operands of an expression are all with rank less
than UINT64/INT64 and the result of the expression is explicitly cast to
UINT64/INT64 to fit the target size.

An example will be:
UINT32 a,b;
// a and b can be any unsigned int type with rank less than UINT64, like
// UINT8, UINT16, etc.
UINT64 c;
c = (UINT64) (a + b);

Some static code checkers may warn that the expression result might
overflow within the rank of "int" (integer promotions) and the result is
then cast to a bigger size.

The commit refines codes by the following rules:
1). When the expression is possible to overflow the range of unsigned int/
int:
c = (UINT64)a + b;

2). When the expression will not overflow within the rank of "int", remove
the explicit type casts:
c = a + b;

3). When the expression will be cast to pointer of possible greater size:
UINT32 a,b;
VOID *c;
c = (VOID *)(UINTN)(a + b); --> c = (VOID *)((UINTN)a + b);

4). When one side of a comparison expression contains only operands with
rank less than UINT32:
UINT8 a;
UINT16 b;
UINTN c;
if ((UINTN)(a + b) > c) {...} --> if (((UINT32)a + b) > c) {...}

For rule 4), if we remove the 'UINTN' type cast like:
if (a + b > c) {...}
The VS compiler will complain with warning C4018 (signed/unsigned
mismatch, level 3 warning) due to promoting 'a + b' to type 'int'.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-06 14:33:26 +08:00
Leo Duran 241f914975 UefiCpuPkg/PiSmmCpuDxeSmm: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables entriees are created or modified.

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-01 12:53:03 +08:00
Leo Duran 787a085b0f UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables are created (S3Resume.c).

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-03-01 12:52:41 +08:00
Jeff Fan 29c90f14c9 UefiCpuPkg/CpuDxe: Do not ASSERT on AllocateMemorySpace() error
Platform PEI may add LOCAL APIC memory mapped space into
EFI_HOB_MEMORY_ALLOCATION. Or platform may allocate this range before.

So, we skip AllocateMemorySpace()'s return status checking. Instead, we add one
DEBUG message for possible trace.

https://bugzilla.tianocore.org/show_bug.cgi?id=390

This updating is suggested by Ersek's comments at
https://www.mail-archive.com/edk2-devel@lists.01.org/msg22585.html

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2017-02-27 10:28:37 +08:00
Jeff Fan af9bce4033 UefiCpuPkg/CpuDxe: Replace EFI_D_xxx with DEBUG_xxx in DEBUG()
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2017-02-24 10:52:40 +08:00
Jeff Fan 7537f8c09a UefiCpuPkg/CpuDxe: Fix hard code actual TimerPeriod value
Current CpuGetTimerValue() implementation return hard code TimerPeriod value. We
could calculate the actual TimerPeriod value over period of time (100us) at the
first time invoking CpuGetTimerValue() and save the TimerPeriod value into one
global variable to avoid delay at the next CpuGetTimerValue() invoking.

https://bugzilla.tianocore.org/show_bug.cgi?id=382

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2017-02-22 15:04:06 +08:00
Jeff Fan 14f92ded90 UefiCpuPkg/CpuDxe: Add Local APIC memory mapped space in GCD
Local APIC memory mapped space should be added into GCD and be allocated.
Otherwise, UEFI firmware cannot get correct memory map for it. For example,
SMM profile feature needs to get the completed MMIO map to protect them.

v2:
  Consume AddMemoryMappedIoSpace() to handle the case that Local APIC
  memory space has already been added before.

https://bugzilla.tianocore.org/show_bug.cgi?id=390

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2017-02-22 14:50:11 +08:00
Jeff Fan 410590f149 UefiCpuPkg/CpuDxe: Copy two functions from PciHostBridge
Copy AddMemoryMappedIoSpace() and IntersectMemoryDescriptor() from
MdeModulePkg\Bus\Pci\PciHostBridgeDxe\PciHostBridge.c.

https://bugzilla.tianocore.org/show_bug.cgi?id=390

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2017-02-22 14:49:53 +08:00
Jiewen Yao 22292ed344 UefiCpuPkg/CpuDxe: Add memory attribute setting.
Add memory attribute setting in CpuArch protocol.
Previous SetMemoryAttributes() API only supports cache attribute setting.

This patch updated SetMemoryAttributes() API to support memory attribute
setting by updating CPU page table.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-02-22 14:07:01 +08:00
Jeff Fan b9d56d0b93 UefiCpuPkg/ExceptionHandlerAsm.S: Fix code length issue with GCC 5.4
X64\ExceptionHandlerAsm.S define MARCO to set up 32 IDT entries header.
It assume GCC compiler will generate the same code length on the following
instrction for each IDT entry.
  jmp    ASM_PFX(CommonInterruptEntry)

It works with GCC 4.x. However, GCC 5.4 will generate different code size of IDT
entry code per the offset value from CommonInterruptEntry address. We should use
DB to make sure each IDT entry header has the same size whatever compiler
version.

.ASM and .nasm used the different solution and do not have this issue.

https://bugzilla.tianocore.org/show_bug.cgi?id=389

Cc: Liming Gao <liming.gao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2017-02-22 09:50:04 +08:00
Leo Duran ff5d3cc25f UefiCpuPkg: Modify CpuIoPei to support new IoLib library
The IO_PPI supports Fifo types by invoking the Fifo routines in the
new BaseIoLibIntrinsic (IoLib class) library.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Leo Duran  <leo.duran@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-01-17 10:10:32 +08:00
Leo Duran 200b4223f0 UefiCpuPkg: Modify CpuIo2Dxe to use new IoLib library
The Fifo routines from the UefiCpuPkg/CpuIo2Dxe driver have been
moved to the new BaseIoLibIntrinsic (IoLib class) library.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Leo Duran  <leo.duran@amd.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2017-01-17 10:10:04 +08:00
Jeff Fan f70174d66f UefiCpuPkg/MpInitLib: Add missing point mark
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
2017-01-16 09:41:01 +08:00
Jeff Fan 8ad05bd26b UefiCpuPkg/MpInitLib: Set initialize value of TimerPeriod
This fix is to pass VS2010/VS2012 build.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Dandan Bi <dandan.bi@intel.com>
2016-12-30 08:39:34 +08:00
Jeff Fan af8ba51aca UefiCpuPkg/MpInitLib: Set new AP to idle state after switching BSP
We need to set new AP to idle state if it is expected to be waken up by new BSP
later.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Kinney Michael D <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-28 15:38:26 +08:00
Jeff Fan b6e45716c3 UefiCpuPkg/MpInitLib: Disable and restore system timer interrupt
We need to disable system timer interrup to avoid generating the pending
interrupt on the old BSP.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Kinney Michael D <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-28 15:38:18 +08:00
Jeff Fan 26b43433c1 UefiCpuPkg/MpInitLib: Swap local APIC timer interrupt state
We need to swap local APIC timer interrupt state between old BSP and new BSP.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Kinney Michael D <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-28 15:38:12 +08:00
Jeff Fan a8d75a1802 UefiCpuPkg/MpInitLib: Move save/restore interrupt to SwitchBSPWorker()
During switching BSP phase, we need to disable CPU interruput to prevent stack
crashed by Timer interrupt handle. But when we enabled source debugging feature,
debug timer interrupt handler (existing on both PEI and DXE) also could crash
the stack used during switching BSP. So,we need to move save/restore interrupt
to SwitchBSPWorker().

Cc: Feng Tian <feng.tian@intel.com>
Cc: Kinney Michael D <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-28 15:38:07 +08:00
Jeff Fan ffab244280 UefiCpuPkg/MpInitLib: Sync BSP's local APIC timer settings to APs
If APs are waken up by INIT-SIPI-SIPI command, they will lose original local
APIC timer setting. As a result, the timer library instance based on local APIC
timer cannot work on APs function.

This fix is to save BSP's local APIC timer settings before waking up APs and
to sync to APs when APs wakeup by INIT-SIPI-SIPI command.

Setting BSP's current counter to AP's initial counter could make sure BSP and
APs have same counter value across BSP switching.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Kinney Michael D <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-28 15:38:02 +08:00
Jeff Fan 43c9fdcccd UefiCpuPkg/DxeMpInitLib: Support source debugging on AP function
The current DxeDebugAgentLib supports source debugging on AP function. This
update is to update DxeMpInitLib to consume Debug Agent Library by
DEBUG_AGENT_INIT_DXE_AP flag. Thus, we could source debugging AP function
invoked by CPU MP Protocol.

However, current SecPeiDebugAgentLib does not support source debugging on AP
function invoked by CPU MP PPI. I have submitted one bugzilla to add this
support at https://bugzilla.tianocore.org/show_bug.cgi?id=308.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Kinney Michael D <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-28 15:37:57 +08:00
Jiewen Yao 31d060d94e UefiCpuPkg/MicrocodeUpdate: Add MP support.
Support the case that BSP and AP are using different Microcode.
The previous logic validates new MCU on BSP only.
The enhanced logic will validate MCU on every BSP and AP.
As long as one processor loads the MCU successfully, it will be updated.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-28 15:09:02 +08:00
Jiewen Yao 2ed658240c UefiCpuPkg/MicrocodeUpdate: enhance flash write logic
The patch updated MicrocodeWrite() to move the Microcode replacement logic
to a standalone function -  UpdateMicrocodeFlashRegion().
More detail description is added in UpdateMicrocodeFlashRegion()
to improve readability.

The Microcode information is collected in InitializeMicrocodeDescriptor(),
so that FmpGetImage() can get the info directly.
MicrocodeRead() is not needed any more.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-28 15:09:01 +08:00
Dandan Bi d0c80b8a2d UefiCpuPkg/SmmCpuFeaturesLib: Fix coding style issues
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-21 11:33:20 +08:00
Dandan Bi ead54b965f UefiCpuPkg: Add Pcd info to uni file
Add PcdCpuSmmStmExceptionStackSize/PcdCpuMsegSize prompt and help
string to uni file.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-21 11:33:18 +08:00
Hao Wu 403f54768c UefiCpuPkg/PiSmmCpuDxeSmm: Add check to avoid NULL ptr dereference
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-20 12:45:26 +08:00
Hao Wu 3b4640ee56 UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii characters
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-20 09:58:13 +08:00
Jiewen Yao d2fc771113 UefiCpuPkg/PiSmmCpu: Add SMM Comm Buffer Paging Protection.
This patch sets the normal OS buffer EfiLoaderCode/Data,
EfiBootServicesCode/Data, EfiConventionalMemory, EfiACPIReclaimMemory
to be not present after SmmReadyToLock.

To access these region in OS runtime phase is not a good solution.

Previously, we did similar check in SmmMemLib to help SMI handler
do the check. But if SMI handler forgets the check, it can still
access these OS region and bring risk.

So here we enforce the policy to prevent it happening.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19 09:37:37 +08:00
Michael Kinney 09119a00cc UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instance
Add a new instances of the SmmCpuFeaturesLib that is used by
platforms to enable the SMI Transfer Monitor(STM) feature.
This new instance is in the same directory as the default
SmmCpuFeaturesLib instance in order to share source files.

The DSC file is updated to build both SmmCpuFeatureLib
instances and to build two versions of the PiSmmCpuDxeSmm
module using each of the SmmCpuFeatureLib instances.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19 09:32:43 +08:00
Michael Kinney 4c6351db25 UefiCpuPkg/SmmCpuFeaturesLib: Split into two files
Split the default implementation of the SmmCpuFeaturesLib
into two files to prepare for the addition of the STM
specific SmmCpuFeaturesLib implementation.  The STM
specific implementation installs a different SMI entry
handler and initialize the MSEG specific MSR at the end
of SmmCpuFeaturesInitializeProcessor().

This patch does not introduce any functional changes
to the default implementation of the SmmCpuFeaturesLib.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19 09:32:38 +08:00
Michael Kinney f7c11c534c UefiCpuPkg: Add STM GUIDs, Protocols, and PCDs
* Add GUIDed HOB that described MSEG region in SMRAM
* Add SM Monitor Init Protocol
* Add PCD to configure size of SMM exception stack
* Add PCD to configure MSEG region size if it is not
  described by the gMsegSmramGuid GUIDed HOB.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19 09:32:34 +08:00
Michael Kinney a03bb3d2a9 UefiCpuPkg/Include: Update MSEG structure comments
Add comments to describe fields of MSEG_HEADER and
add define values for the MonitorFeatures field.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19 09:32:27 +08:00
Hao Wu 14806d7b7d UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176

Update CPUID leaf and sub-leaf indexes and structures as described by
Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A, September 2016, CPUID instruction.

Summary of incompatible changes:
1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed
from 'PQE' to 'RDT_A'.

2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to
'CPUID_INTEL_RDT_MONITORING'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'.

3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement
Information' related definitions
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to
'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'.
Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been
renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'.

This commit also updates the relating codes in
UefiCpuPkg/Application/Cpuid to reflect the changes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16 11:48:21 +08:00
Hao Wu 35fd9411d0 UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176

Add the MSR header file of Goldmont processor according to Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016,
Chapter 35 Model-Specific-Registers (MSR), Section 35.5.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16 11:48:15 +08:00
Hao Wu 37cea63f17 UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176

Update the MSR header file of Skylake processor according to Intel(R) 64
and IA-32 Architectures Software Developer's Manual, Volume 3, September
2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15.

Summary of incompatible changes:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to
IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16 11:48:12 +08:00
Hao Wu 0f16be6d9e UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)
https://bugzilla.tianocore.org/show_bug.cgi?id=176

Update MSR header files of processors (excluding Goldmont and Skylake
processors) according to Intel(R) 64 and IA-32 Architectures Software
Developer's Manual, Volume 3, September 2016, Chapter 35
Model-Specific-Registers (MSR).

Summary of incompatible changes:
General:
1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header
files has been removed or renamed to IA32_PERF_GLOBAL_STATUS
Typo 'STAUS' has been fixed in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.

2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS)
in processor-specific header files have been removed or renamed to
IA32_MC{X}_{XXX} (like IA32_MC4_STATUS)
Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM.
If the MSR definition is the same with architectural MSR, we remove it.
Otherwise, we rename the MSR.
Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in
SDM are still kept in processor-specific header files.

HaswellMsr.h:
1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed
Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE'
in SDM.
Since the MSR definition is the same with architectural MSR, we remove it.

SandyBridgeMsr.h:
1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields
0:3
Bit description change from 'Core {X} select' to 'Slice {X} select' for
bit 0:3 in SDM.

SilvermontMsr.h:
1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed
Bit description for this MSR is totally changed in SDM, we modify the
structure definition to align with it.

XeonDMsr.h:
1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY
and MSR_PKG_C10_RESIDENCY have been removed
Those 3 MSRs are not defined for this processor in SDM, we remove them.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16 11:48:08 +08:00
Feng Tian b6fea56cb5 UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failure
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-16 08:27:59 +08:00
Dandan Bi 499ed484e8 UefiCpuPkg/Capsule: Fix coding style issues
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14 21:34:44 +08:00
Dandan Bi 764b294f11 UefiCpuPkg/MicrocodeUpdateDxe: Fix coding style issues in INF file
1. Add MicrocodeUpdate.h to the [Sources] section.
2. Fix the incorrect Guid/Protocol format issues.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14 21:34:44 +08:00
Dandan Bi 664e3a0b9f UefiCpuPkg: Add info string to UNI file for PcdCpuSmmStaticPageTable
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14 21:34:43 +08:00
Dandan Bi 367284e773 UefiCpuPkg: Make the comments align with the functions
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-14 21:34:42 +08:00
Michael Kinney 854c6b80dc UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRR field from PSD
https://bugzilla.tianocore.org/show_bug.cgi?id=277

The MTRR field was removed from PROCESS_SMM_DESCRIPTOR
structure in commit:

26ab5ac362

However, the references to the MTRR field in assembly
files were not removed.  Remove the extern reference
to gSmiMtrr and set the Reserved14 field
of PROCESS_SMM_DESCRIPTOR to 0.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-06 23:34:16 -08:00
Michael Kinney a6b7bc7a87 UefiCpuPkg/PiSmmCpuDxeSmm: Always initialze PSD
The following commit moved the initialization of the
default PROCESSOR_SMM_DESCRIPTOR from MpService.c to
SmramSaveState.c and made this initialization
conditional on the value returned by the
SmmCpuFeaturesGetSmiHandlerSize() library function.

f12367a0b1

This changed the behavior of the PiSmmCpuDxeSmm module.
The initialization of the PROCESSOR_SMM_DESCRIPTOR is
moved before the call to SmmCpuFeaturesGetSmiHandlerSize()
to preserve the previous behavior.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-06 23:26:31 -08:00
Jiewen Yao e4435f710c UefiCpuPkg/PiSmmCpu: Fixed #double fault on #page fault.
This patch fixes https://bugzilla.tianocore.org/show_bug.cgi?id=246

Previously, when SMM exception happens after EndOfDxe,
with StackGuard enabled on IA32, the #double fault exception
is reported instead of #page fault.

Root cause is below:

Current EDKII SMM page protection will lock GDT.
If IA32 stack guard is enabled, the page fault handler will do task switch.
This task switch need write busy flag in GDT, and write TSS.

However, the GDT and TSS is locked at that time, so the
double fault happens.

We decide to not lock GDT for IA32 StackGuard enabled.

This issue does not exist on X64, or IA32 without StackGuard.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-12-07 13:13:55 +08:00
Michael Kinney 831d287a99 UefiCpuPkg/Include: Add VMX MSR register structures
https://bugzilla.tianocore.org/show_bug.cgi?id=279

Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER
structures with the bit fields for these two MSRs.   Also
add MSEG_HEADER structure whose base address is in the
MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-01 11:58:02 -08:00
Michael Kinney f12367a0b1 UefiCpuPkg/PiSmmCpuDxeSmm: Remove PSD layout assumptions
https://bugzilla.tianocore.org/show_bug.cgi?id=277

Remove dependency on layout of PROCESSOR_SMM_DESCRIPTOR
everywhere possible.  The only exception is the standard
SMI entry handler template that is included with the
PiSmmCpuDxeSmm module.  This allows an instance of the
SmmCpuFeaturesLib to provide alternate
PROCESSOR_SMM_DESCRIPTOR structure layouts.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-01 11:07:13 -08:00
Michael Kinney 26ab5ac362 UefiCpuPkg/PiSmmCpuDxeSmm: Remove MTRRs from PSD structure
https://bugzilla.tianocore.org/show_bug.cgi?id=277

All CPUs use the same MTRR settings.  Move MTRR settings
from a field in the PROCESSOR_SMM_DESCRIPTOR structure into
a module global variable.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-01 11:07:03 -08:00
Jeff Fan 396fe30ad9 UefiCpuPkg/CpuExceptionHandlerLib: remove un-used mReservedVectors
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-01 16:03:20 +08:00
Jeff Fan 368c54e718 UefiCpuPkg: Add ExceptionHandlerData for ArchRestoreExceptionContext()
mReservedVectors is not set, we could add parameter ExceptionHandlerData for
ArchRestoreExceptionContext() that could use it instead of mReservedVectors.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-01 16:03:16 +08:00
Jeff Fan 81b21fc250 UefiCpuPkg: Add ExceptionHandlerData for ArchSaveExceptionContext()
mReservedVectors is not set, we could add parameter ExceptionHandlerData for
ArchSaveExceptionContext() that could use it instead of mReservedVectors.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-01 16:03:13 +08:00
Jeff Fan 56e4a7d726 UefiCpuPkg/PiSmmCpuDxeSmm: Clear some semaphores on S3 boot path
Some semaphores are not cleared on S3 boot path. For example,
mSmmMpSyncData->CpuData[CpuIndex].Present. It may still keeps the value set at
SMM runtime during S3 resume. It may causes BSP have the wrong judgement on SMM
AP's present state.

We have one related fix at e78a2a49ee. But that is
not completed.

This fix is to clear Busy/Run/Present semaphores in InitializeMpSyncData().

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-01 15:22:02 +08:00
Jiewen Yao bcc6a38f4c UefiCpuPkg/MicrocodeUpdate: Fix GetImage API
Current GetImage API forgets to return data to caller.

Add code to fix it.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-30 20:13:58 +08:00
Jiewen Yao e50f951286 UefiCpuPkg/PiSmmCpu: relax superpage protection on page split.
PiSmmCpu driver may split page for page attribute request.
Current logic not only propagates the super page attribute to
the leaf page attribut, but also to the directory page attribute.

However, the later might be wrong because we cannot clear protection
without touching directory page attribute.
The effective protection is the strictest combination
across the levels.

We should always clear protection on directory page and set
protection on leaf page for easy clearing later.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-30 20:12:43 +08:00
Laszlo Ersek 6e1987f19a UefiCpuPkg/MpInitLib: wait no longer than necessary for initial AP startup
Sometimes a platform knows exactly how many CPUs it has at boot. It should
be able to
- set PcdCpuMaxLogicalProcessorNumber dynamically to this number,
- set PcdCpuApInitTimeOutInMicroSeconds to a very long time (for example
  MAX_UINT32, approx. 71 minutes),
- and expect that MpInitLib wait exactly as long as necessary for all APs
  to report in.

Other platforms should be able to continue setting a reasonably large
upper bound on supported CPUs, and waiting for a reasonable, fixed amount
of time for all APs to report in.

Add this functionality. The TimedWaitForApFinish() function will return
when all APs have reported in, or the timeout has expired -- whichever
happens first.

(Accessing these PCDs dynamically is safe. The PEI and DXE phase instances
of this library are restricted to PEIM and DXE_DRIVER client modules, thus
the PCD accesses cannot be linked into runtime code.)

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=116
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-29 10:05:52 +01:00
Laszlo Ersek bb767506b2 UefiCpuPkg/PiSmmCpuDxeSmm: handle dynamic PcdCpuMaxLogicalProcessorNumber
"UefiCpuPkg/UefiCpuPkg.dec" already allows platforms to make
PcdCpuMaxLogicalProcessorNumber dynamic, however PiSmmCpuDxeSmm does not
take this into account everywhere. As soon as a platform turns the PCD
into a dynamic one, at least S3 fails. When the PCD is dynamic, all
PcdGet() calls translate into PCD DXE protocol calls, which are only
permitted at boot time, not at runtime or during S3 resume.

We already have a variable called mMaxNumberOfCpus; it is initialized in
the entry point function like this:

> //
> // If support CPU hot plug, we need to allocate resources for possibly
> // hot-added processors
> //
> if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
>   mMaxNumberOfCpus = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
> } else {
>   mMaxNumberOfCpus = mNumberOfCpus;
> }

There's another use of the PCD a bit higher up, also in the entry point
function:

> //
> // Use MP Services Protocol to retrieve the number of processors and
> // number of enabled processors
> //
> Status = MpServices->GetNumberOfProcessors (MpServices, &mNumberOfCpus,
>                        &NumberOfEnabledProcessors);
> ASSERT_EFI_ERROR (Status);
> ASSERT (mNumberOfCpus <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));

Preserve these calls in the entry point function, and replace all other
uses of PcdCpuMaxLogicalProcessorNumber -- there are only reads -- with
mMaxNumberOfCpus.

For PcdCpuHotPlugSupport==TRUE, this is an unobservable change.

For PcdCpuHotPlugSupport==FALSE, we even save SMRAM, because we no longer
allocate resources needlessly for CPUs that can never appear in the
system.

PcdCpuMaxLogicalProcessorNumber is also retrieved in
"UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c",  but only in
the library instance constructor, which runs even before the entry point
function is called.

Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=116
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-28 12:19:40 +01:00
Jeff Fan f17e28c791 UefiCpuPkg/DxeMpLib: Remove unnecessary ret instruction
Reported-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-28 08:57:09 +08:00
Jeff Fan f56379f361 UefiCpuPkg/DxeMpLib: Fix bug when getting target C-State from eax
AP will get target C-State from eax[7:4]. We do shift in ebx firstly before set
to eax. It will lead ebx is incorrect in the next time.

The fix is to set ebx to eax firstly and does shift in eax. Thus, ebx could keep
original value.

Reported-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-28 08:56:48 +08:00
Jeff Fan 9f91cb01c4 UefiCpuPkg/DxeMpLib: Make sure APs in safe loop code
Add one semaphore to make sure BSP to wait till all APs run in AP safe loop
code.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-28 08:56:40 +08:00
Jeff Fan bf2786dc79 UefiCpuPkg/DxeMpLib: Allocate new safe stack < 4GB
For long mode DXE, we will disable paging on AP to protected mode to execute AP
safe loop code in reserved memory range under 4GB. But we forget to allocate
stack for AP under 4GB and AP still are using original AP stack. If original AP
stack is larger than 4GB, it cannot be used after AP is transferred to protected
mode. Besides MwaitSupport == TRUE, AP stack is still required during phase of
disabling paging in long mode DXE.

Moreover, even though AP stack is always under 4GB (a) in Ia32 DXE and (b) with
this patch, after transferring to protected mode from X64 DXE, AP stack
(in BootServiceData) maybe crashed by OS after Exit Boot Service event.

This fix is to allocate reserved memory range under 4GB together with AP safe
loop code. APs will switch to new stack in safe loop code.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-28 08:56:36 +08:00
Jeff Fan 081f6416ff UefiCpuPkg/DxeMpLib: Get safe AP loop handler from global variable
AP loop function is already saved into global variable, needn't to get it from
AP function parameter.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-28 08:56:26 +08:00
Jiewen Yao 7fa1376c5c UefiCpuPkg/PiSmmCpu: Correct exception message.
This patch fixes the first part of
https://bugzilla.tianocore.org/show_bug.cgi?id=242

Previously, when SMM exception happens, "stack overflow" is misreported.
This patch checked the PF address to see it is stack overflow, or
it is caused by SMM page protection.

It dumps exception data, PF address and the module trigger the issue.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-24 10:51:16 +08:00
Laszlo Ersek 1cbd833089 UefiCpuPkg/MpInitLib: fix feature test for Extended Topology CPUID leaf
According to the Intel SDM (325462-060US / September 2016),

> INPUT EAX = 0BH: Returns Extended Topology Information
>
> [...] Software must detect the presence of CPUID leaf 0BH by verifying
> (a) the highest leaf index supported by CPUID is >= 0BH, and
> (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...]

The "GetApicId" sections in the Ia32 and X64 "MpFuncs.nasm" files do not
perform check (b).

This causes an actual bug in the following OVMF setup:

- Intel W3550 host processor <http://ark.intel.com/products/39720/>,

- the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU
  visible to the guest should be exactly the same as the host CPU".

Under "GetApicId", check (a) passes: the CPUID level of the W3550 is
exactly 11 decimal. However, leaf 11 itself is not supported, therefore
EDX is set to zero:

> If a value entered for CPUID.EAX is less than or equal to the maximum
> input value and the leaf is not supported on that processor then 0 is
> returned in all the registers.

Because we don't check (b), the "GetProcessorNumber" section of the code
is reached with an initial APIC ID of 0 in EDX on all of the APs. Given
that "GetProcessorNumber" searches the
"MP_CPU_EXCHANGE_INFO.CpuInfo[*].InitialApicId" fields for a match, all
APs enter ApWakeupFunction() with an identical "NumApsExecuting"
parameter. This results in unpredictable guest behavior (crashes, reboots,
hangs etc).

Reorganize the "GetApicId" section and add the missing check in both
assembly files.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-23 21:41:24 +01:00
Laszlo Ersek 4af3ae1463 UefiCpuPkg/LocalApicLib: fix feature test for Extended Topology CPUID leaf
According to the Intel SDM (325462-060US / September 2016),

> INPUT EAX = 0BH: Returns Extended Topology Information
>
> [...] Software must detect the presence of CPUID leaf 0BH by verifying
> (a) the highest leaf index supported by CPUID is >= 0BH, and
> (b) CPUID.0BH:EBX[15:0] reports a non-zero value. [...]

The LocalApicLib instances in UefiCpuPkg do not perform check (b).

This causes an actual bug in the following OVMF setup:

- Intel W3550 host processor <http://ark.intel.com/products/39720/>,

- the QEMU/KVM guest's VCPU model is set to "host", that is, "the CPU
  visible to the guest should be exactly the same as the host CPU".

In the GetInitialApicId() function, check (a) passes: the CPUID level of
the W3550 is exactly 11 decimal. However, leaf 11 itself is not supported,
therefore EDX is set to zero:

> If a value entered for CPUID.EAX is less than or equal to the maximum
> input value and the leaf is not supported on that processor then 0 is
> returned in all the registers.

Because we don't check (b), we return 0 as initial APIC ID on the BSP and
on all of the APs as well.

Add the missing check.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-23 21:41:05 +01:00
Laszlo Ersek b43dd22981 UefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncTimeout, PcdCpuSmmSyncMode
Move the declaration of these PCDs from the

  [PcdsFixedAtBuild, PcdsPatchableInModule]

section of "UefiCpuPkg/UefiCpuPkg.dec" to the

  [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]

section. Their types, default values, and token values remain unchanged.

Only UefiCpuPkg/PiSmmCpuDxeSmm consumes these PCDs, specifically on the
call stack of its entry point function, and it turns them into static or
dynamically allocated data in SMRAM:

  PiCpuSmmEntry()                            [PiSmmCpuDxeSmm.c]
    InitializeSmmTimer()                     [SyncTimer.c]
      PcdCpuSmmApSyncTimeout
      -> mTimeoutTicker
    InitializeMpServiceData()                [MpService.c]
      InitializeMpSyncData()                 [MpService.c]
        PcdCpuSmmSyncMode
        -> mSmmMpSyncData->EffectiveSyncMode

However, there's another call path to fetching "PcdCpuSmmSyncMode", namely

  SmmInitHandler()                           [PiSmmCpuDxeSmm.c]
    InitializeMpSyncData()                   [MpService.c]
      PcdCpuSmmSyncMode
      -> mSmmMpSyncData->EffectiveSyncMode

and this path is exercised during S3 resume (as stated by the comment in
SmmInitHandler() too, "Initialize private data during S3 resume").

While we can call the PCD protocol (via PcdLib) for fetching dynamic PCDs
in the entry point function, we cannot do that at S3 resume. Therefore
pre-fetch PcdCpuSmmSyncMode into a new global variable (which lives in
SMRAM) in InitializeMpServiceData(), just before calling
InitializeMpSyncData(). This way InitializeMpSyncData() can retrieve the
stashed PCD value from SMRAM, regardless of the boot mode.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=230
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-22 09:02:54 +01:00
Jiewen Yao 750ec4cabd UefiCpuPkg/PiSmmCpu: Check XdSupport before set NX.
When XD is not supported, the BIT63 is reserved.
We should not set BIT63 in the page table.

Test OVMF IA32/IA32X64 with XD enabled/disabled.

Analyzed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-18 10:53:59 +08:00
Jeff Fan ec16deeac9 UefiCpuPkg/SecCore: Correct print format for stack information
v2:
  Per Laszlo and Andrew's comments at
    https://lists.01.org/pipermail/edk2-devel/2016-November/004759.html
  SecCoreData->StackBase is VOID * type. We should use %p to dump VOID * type.
  SecCoreData->StackSize is UINTN type, but %x only could print unsinged-int
  type. We will cast it to UINT32 firstly and then use %x to print it.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-11-18 09:43:53 +08:00
Jeff Fan 5c88af795d MdeModulePkg/PiSmmCpuDxeSmm: Check RegisterCpuInterruptHandler status
Once platform selects the incorrect instance, the caller could know it from
return status and ASSERT().

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-18 09:43:52 +08:00
Michael Kinney c773514d45 UefiCpuPkg/PiSmmCpuDxeSmm: Add volatile to mNumberToFinish
Add volatile qualifier to mNumberToFinish to prevent GCC 5.4
compiler from optimizing away required logic in ACPI S3 resume.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17 17:37:50 -08:00
Michael Kinney 672b80c8b7 UefiCpuPkg/PiSmmCpuDxeSmm: TransferApToSafeState() use UINTN params
Update TransferApToSafeState() use UINTN params to reduce the
number of type casts required in these calls.  Also change
the NumberToFinish parameter from UINT32* to UINTN
NumberToFinishAddress to resolve issues with conversion from
a volatile pointer to a non-volatile pointer.  The assembly
code that receives the NumberToFinishAddress value must treat
that memory location as a volatile to track the number of APs.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17 17:37:50 -08:00
Laszlo Ersek dd3fa0cd72 UefiCpuPkg/MpInitLib: support 64-bit AP stack addresses
The cached "CPU_INFO_IN_HOB.ApTopOfStack" field currently has type UINT32.
This is not ideal because the AP stacks are located within
"CpuMpData->Buffer", which is allocated with a plain AllocatePages() call
in MpInitLibInitialize():

  platform  CpuMpPei included  PEI RAM > 4GB  result
  --------  -----------------  -------------  ------
  Ia32      *                  n/a            good
  Ia32X64   no                 n/a            BAD
  Ia32X64   yes                n/a            good
  X64       no                 *              BAD
  X64       yes                no             good
  X64       yes                yes            BAD

- If we are on an Ia32X64 or X64 platform that does not include CpuMpPei,
  then CpuDxe cannot reuse the CPU_INFO_IN_HOB structures preallocated by
  CpuMpPei (through the CpuInitMpLib GUID HOB), and then AllocatePages()
  -- invoked first in 64-bit DXE -- could return an address outside of
  32-bit address space.

- If we are on an X64 platform where the permanent PEI RAM extends above
  the 32-bit address space, then the same issue can surface even if
  CpuMpPei is included: even the original allocation of the
  CPU_INFO_IN_HOB structures, by CpuMpPei, could be satisfied from above
  4GB.

The original "AP init" branch in "X64/MpFuncs.nasm" correctly considers a
64-bit stack start: the "MP_CPU_EXCHANGE_INFO.StackStart" field has type
UINTN, and the code uses QWORD addition and movement to set RSP from it.

Adapt the "GetApicId" branch of "X64/MpFuncs.nasm":

- change the type of "CPU_INFO_IN_HOB.ApTopOfStack" to UINT64,

- remove the explicit truncation to UINT32 in InitializeApData(),

- update the "GetNextProcNumber" iteration size to the new size of
  "CPU_INFO_IN_HOB",

- set RSP with a QWORD movement from "CPU_INFO_IN_HOB.ApTopOfStack".

Because the same CPU_INFO_IN_HOB structure is used by "Ia32/MpFuncs.nasm",
we have to update the "GetNextProcNumber" iteration size there as well.
The ESP setting can be preserved as a DWORD movement from the original
offset (decimal 12), since our integers are little endian.

Cc: Jeff Fan <jeff.fan@intel.com>
Fixes: 845c5be1fd
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17 10:58:18 +01:00
Laszlo Ersek 00650c531a UefiCpuPkg/MpInitLib/X64/MpFuncs.nasm: fix fatal typo
The recent patch "UefiCpuPkg/MpInitLib: Program AP stack in fixed address"
inadvertently broke the first startup of APs during X64 PEI, because in
the TestLock section of the code, it replaced the access to the
NumApsExecuting counter with an access to the unrelated InitFlag field.

Cc: Jeff Fan <jeff.fan@intel.com>
Fixes: 845c5be1fd
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17 10:58:07 +01:00
Laszlo Ersek 5797f61c55 UefiCpuPkg/MpInitLib/X64/MpFuncs.nasm: remove superfluous instruction
At this point, ESI still has the value from EBX.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17 10:57:57 +01:00
Laszlo Ersek 3a9aa635be UefiCpuPkg/DxeMpInitLib: remove duplicate HobLib class dependency
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17 10:57:33 +01:00
Jiewen Yao 717fb60443 UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection.
PiSmmCpuDxeSmm consumes SmmAttributesTable and setup page table:
1) Code region is marked as read-only and Data region is non-executable,
if the PE image is 4K aligned.
2) Important data structure is set to RO, such as GDT/IDT.
3) SmmSaveState is set to non-executable,
and SmmEntrypoint is set to read-only.
4) If static page is supported, page table is read-only.

We use page table to protect other components, and itself.

If we use dynamic paging, we can still provide *partial* protection.
And hope page table is not modified by other components.

The XD enabling code is moved to SmiEntry to let NX take effect.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2016-11-17 16:30:07 +08:00
Jiewen Yao 28b020b5de UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable.
If enabled, SMM will not use on-demand paging.
SMM will build static page table for all memory.

The page table size depend on 2 things:
1) The 1G paging capability.
2) The whole system memory/MMIO addressing capability.

A) If the system only supports 2M paging,
When the whole memory/MMIO is 32bit, we only need 1+1+4=6 pages for 4G.
When the whole memory/MMIO is 39bit, we need 1+1+256 pages (~ 1M)
When the whole memory/MMIO is 48bit, we need 1+256+256*256 pages (~ 257M)

B) If the system supports 1G paging.
When the whole memory/MMIO is 32bit, we only need 1+1+4=6 pages for 4G.
(We still generate 2M page for maintenance consideration.)
When the whole memory/MMIO is 39bit, we still need 6 pages.
(We setup 1G paging for >1G.)
When the whole memory/MMIO is 48bit, we need 1+256 pages (~ 1M).

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2016-11-17 16:30:05 +08:00
Jeff Fan b3775af277 UefiCpuPkg/MpInitLib: Update AP information when BSP switched
When BSP switched, we need to update some AP information. For example,
ApStartupSignalBuffer and ApTopOfStack.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16 16:28:22 +08:00
Jeff Fan 845c5be1fd UefiCpuPkg/MpInitLib: Program AP stack in fixed address
Currently, MpInitLib will program AP stack in dynamic address. Each processor
will calculate its stack address by adding stack size based on the last stack
address. That means AP may have the different stack address everytime it is
wakeup by INIT-SIPI-SIPI.

When all APs have wakeup to execute AP task, each each has been assigned one
stack address. Once the timeout happened on some of APs, BSP will send INIT-
SIPI-SIPI to wake up APs. We need to re-assign stack for APs. Based on the
current implementation, we might assign one stack address used by other APs.
It will cause the unexpected stack overlapped issue.

This fix changed the stack assignment policy. We will record the stack address
assigned to AP at first time AP wakeup. When AP failed on AP task, BSP could
reassigned the same stack for it.

Getting initial APIC ID in assembly code could help AP to get saved its stack
address.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16 16:28:22 +08:00
Jeff Fan 46d4b8858f UefiCpuPkg/MpInitLib: Add InitFlag and CpuInfo in MP_CPU_EXCHANGE_INFO
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16 16:28:21 +08:00
Jeff Fan 31a1e4da49 UefiCpuPkg/MpInitLib: Remove CPU information from CPU_AP_DATA
Some CPU information (InitialApicId/ApicId/Health) are duplicated in CPU_AP_DATA
and CPU_INFO_IN_HOB.

This update is to remove the ones from CPU_AP_DATA and update MpInitLib to
consume the ones from CPU_INFO_IN_HOB.

V2:
  Fixed potential un-initialized variable issue.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16 16:28:02 +08:00
Jeff Fan cb33bde4ac UefiCpuPkg/MpInitLib: Force sending INIT-SIPI-SIPI to reset APs
If BSP found APs timeout happened when AP executing AP task, BSP will reset APs
by WakeUpAP(). However, if ApLoopMode is ApMwaitLoop or ApRunLoop, WakeUpAp()
will try to write semaphore in memory to wake up AP. It cannot wake up APs
actually if APs still executing AP task.

This fix is to set ApInitReconfig flag to force BSP to send INIT-SIPI-SIPI to
wake up APs.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16 16:09:08 +08:00
Jeff Fan d67cbc6604 UefiCpuPkg/MpInitLib: Fixed offset error on Cr3Location
Cr3Location offset value should be 0x34 not 0x3C.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-16 16:09:04 +08:00
Jeff Fan e242cdfb30 UefiCpuPkg/PiSmmCpuDxeSmm: Free SmramRanges to save SMM space
Cc: Zeng Star <star.zeng@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Zeng Star <star.zeng@intel.com>
2016-11-16 16:01:14 +08:00
Jeff Fan ec8a387700 UefiCpuPkg/PiSmmCpuDxeSmm: Decrease mNumberToFinish in AP safe code
We will put APs into hlt-loop in safe code. But we decrease mNumberToFinish
before APs enter into the safe code. Paolo pointed out this gap.

This patch is to move mNumberToFinish decreasing to the safe code. It could
make sure BSP could wait for all APs are running in safe code.

https://bugzilla.tianocore.org/show_bug.cgi?id=216

Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-15 09:47:32 +08:00
Jeff Fan 45e3440ac2 UefiCpuPkg/PiSmmCpuDxeSmm: Place AP to 32bit protected mode on S3 path
On S3 path, we may transfer to long mode (if DXE is long mode) to restore CPU
contexts with CR3 = SmmS3Cr3 (in SMM). AP will execute hlt-loop after CPU
contexts restoration. Once one NMI or SMI happens, APs may exit from hlt state
and execute the instruction after HLT instruction. If APs are running on long
mode, page table is required to fetch the instruction. However, CR3 pointer to
page table in SMM. APs will crash.

This fix is to disable long mode on APs and transfer to 32bit protected mode to
execute hlt-loop. Then CR3 and page table will no longer be required.

https://bugzilla.tianocore.org/show_bug.cgi?id=216

Reported-by: Laszlo Ersek <lersek@redhat.com>
Analyzed-by: Paolo Bonzini <pbonzini@redhat.com>
Analyzed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-15 09:47:32 +08:00
Jeff Fan 4a0f88dd64 UefiCpuPkg/PiSmmCpuDxeSmm: Put AP into safe hlt-loop code on S3 path
On S3 path, we will wake up APs to restore CPU context in PiSmmCpuDxeSmm
driver. However, we place AP in hlt-loop under 1MB space borrowed after CPU
restoring CPU contexts.
In case, one NMI or SMI happens, APs may exit from hlt state and execute the
instruction after HLT instruction. But the code under 1MB is no longer safe at
that time.

This fix is to allocate one ACPI NVS range to place the AP hlt-loop code. When
CPU finished restoration CPU contexts, AP will execute in this ACPI NVS range.

https://bugzilla.tianocore.org/show_bug.cgi?id=216

v2:
  1. Make stack alignment per Laszlo's comment.
  2. Trim whitespace at end of end.
  3. Update year mark in file header.

Reported-by: Laszlo Ersek <lersek@redhat.com>
Analyzed-by: Paolo Bonzini <pbonzini@redhat.com>
Analyzed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-15 09:44:53 +08:00
Jeff Fan 8677a56af6 UefiCpuPkg/DxeMpLib: Place APs to suitable state on Legacy OS boot
Currently, DxeMpLib only places APs into specified c-state in Exit Boot Service
callback function for UEFI OS boot. We need to put APs into specified c-state
for legacy OS boot also.

https://bugzilla.tianocore.org/show_bug.cgi?id=210

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-14 09:56:59 +08:00
Jeff Fan 86af2eb8b4 UefiCpuPkg/DxeMpLib: Rename MpInitExitBootServicesCallback()
Rename MpInitExitBootServicesCallback() to MpInitChangeApLoopCallback() because
it will not only be invoked on Exit Boot Service Event, but also will be invoked
on Legacy Ready To Boot Event.

https://bugzilla.tianocore.org/show_bug.cgi?id=210

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-14 09:56:26 +08:00
Jeff Fan ffd6b0b1b6 UefiCpuPkg/DxeMpLib: Allocate below 4GB mem for AsmRelocateApLoopFunc
Current implementation just allocates reserve memory for AsmRelocateApLoopFunc.
It not be safe because APs will be placed into 32bit protected mode on long mode
DXE. This reserve memory must be located below 4GB memory.

This fix is to allocate < 4GB memory for AsmRelocateApLoopFunc.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
[lersek@redhat.com: strip whitespace at EOL]
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-11-11 12:26:00 +01:00
Jeff Fan 14e8137c82 UefiCpuPkg/MpInitLib: Do not wakeup AP if only one processor supported
If MaxLogicalProcessorNumber is only 1, we needn't to wake up APs at all
and needn't to register callback functions.

It could improve boot performance on single supported system.

https://bugzilla.tianocore.org/show_bug.cgi?id=204

Cc: Feng Tian <feng.tian@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-09 16:01:13 +08:00
Jeff Fan af34c10649 UefiCpuPkg: Display new stack base and size
Dump new stack base and size information could help developer to narrow down
stack crash issue.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-09 16:00:15 +08:00
Jiewen Yao bb7c65bd03 UefiCpuPkg/MicrocodeUpdate: Add Microcode FMP build sample
This folder provides the sample build for Microcode FMP.
The DSC/FDF is to convert the Microcode binary/text to Microcode FMP.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:43:24 +08:00
Jiewen Yao 882668595c UefiCpuPkg/MicrocodeUpdate: Add MicrocodeUpdate component.
MicrocodeUpdate supports update Microcode region via UEFI FMP capsule.

MicrocodeUpdate SetImage() will perform the Microcode version,
ProcessorSignature/ProcessorFlag, and try to load microcode.
If and only if the Microcode is loaded successfully, and new Microcode
will be updated to system flash region.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:43:22 +08:00
Jiewen Yao c7829aa0e9 UefiCpuPkg/MicrocodeFlashAccessLib: Add NULL MicrocodeFlashAccessLib.
Add NULL instance to pass build.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:43:20 +08:00
Jiewen Yao 90c45da449 UefiCpuPkg/UefiCpuPkg.dec: Add Microcode capsule related definition.
1) Add Microcode capsule related GUID.
   gMicrocodeFmpImageTypeIdGuid
2) Add Microcode capsule related library.
   MicrocodeFlashAccessLib

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:43:18 +08:00
Jiewen Yao faf2c63b4a UefiCpuPkg/Include: Add MicrocodeFlashAccessLib header.
This library is used to abstract microcode flash region access.
This library is consumed by a microcode capsule update module.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:43:16 +08:00
Jiewen Yao cc0c03874a UefiCpuPkg/Include: Add Microcode FMP definition.
It defined ImageTypeId for Microcode.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:43:15 +08:00
Jiewen Yao 5c7cf1cc9e UefiCpuPkg/UefiCpuPkg.dsc: Add MicrocodeCapsule related component.
Add Microcode capsule related component to check build.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-08 22:40:43 +08:00
Liming Gao b782753fa2 UefiCpuPkg PeiCpuExceptionHandlerLib: Add the missing nasm files in INF
All CpuExceptionHandlerLib library instances use nasm source files.

Cc: Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-03 10:28:40 +08:00
Jeff Fan 1c8ca9a012 UefiCpuPkg/LocalApicLib: Add EFIAPI for GetProcessorLocationByApicId()
We need to add EFIAPI for all interface service including library API.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leo Duran  <leo.duran@amd.com>
Cc: Michael Kinney <Michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Leo Duran  <leo.duran@amd.com>
2016-11-02 09:17:04 +08:00
Jeff Fan 262128e5ab UefiCpuPkg/LocalApicLib: Rename GetProcessorLocation()
GetProcessorLocation() is too generic and will conflict with the API defined in
Galileo Board Software Package v1.0.0.

This update is just to rename GetProcessorLocation() to one specific name
GetProcessorLocationByApicId().

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leo Duran  <leo.duran@amd.com>
Cc: Michael Kinney <Michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Leo Duran  <leo.duran@amd.com>
2016-11-02 09:16:21 +08:00
Leo Duran 73152f19c0 UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran  <leo.duran@amd.com>
Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-01 09:08:45 +08:00
Gary Lin 438f17665c UefiCpuPkg: Fix typos in comments
- excute -> execute
- Retrive -> Retrieve
- possilbe -> possible
- CONTINOUS -> CONTINUOUS
- storgage -> storage
- allcated -> allocated
- triggerred -> triggered
- paramter -> parameter
- perodically -> periodically
- retore -> restore

v2:
- ruturn -> return

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gary Lin <glin@suse.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-10-24 09:09:48 +08:00
Jeff Fan d93a10c02b UefiCpuPkg/Cpuid: Remove wrong while-loop check after for-loop
while-loop check should not co-exist with for-loop. This should be typo when we
check-in the original code. We should keep one loop only.

This issue caused CLANG38 build failure reported by
https://tianocore.acgmultimedia.com/show_bug.cgi?id=148

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-10-18 09:15:44 +08:00
Jeff Fan 93638568c1 UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIs
Currently, this is ASSERT() if neither SecPlatformInformation2 nor
SecPlatformInformation PPIs are found. This is not correct. Per PI specification
both of them are optional PPI. Platform may not install them.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-21 14:12:49 +08:00
Jeff Fan 030d2de7c7 UefiCpuPkg/SecCore: Fix comment typo
Revert SecPlatformInformation2 and SecPlatformInformation in two comment blocks.
And correct the words.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-21 14:12:45 +08:00
Jeff Fan 8a5b8cef67 UefiCpuPkg/SecCore: Re-install SEC platform information(2) PPI
In SecTemporaryRamDone(), we will build one privated GUIDed-HOB to save CPU BIST
Data and re-install SEC platform information(2) PPI. Then other PEI drivers
could get CPU BIST data from the private GUIDed-HOB by new installed PPI.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:46 +08:00
Jeff Fan d157de8b56 UefiCpuPkg/SecCore: Abstract worker function GetBistFromHob()
Abstract one worker function to get CPU BIST from the GUIDed-HOB. Add
SecPlatformInformationBist() and SecPlatformInformation2Bist() to invoke
GetBistFromHob(). Add in/out for parameter in function header.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:42 +08:00
Jeff Fan 863c738c4a UefiCpuPkg/SecCore: Add SecBist.c
Add SecBist.c and copy GetBistInfoFromPpi() and SecPlatformInformation2() from
UefiCpuPkg/CpuMpPei/CpuBist.c. And update SecMain.c, SecMain.inf and
UefiCpuPkg.dsc accordinlgy to pass build.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:39 +08:00
Jeff Fan 8643299420 UefiCpuPkg/CpuMpPei: Build GUIDed-HOB to store all CPU BIST Data
Build gEfiSecPlatformInformation2PpiGuid GUIDed-HOB to store all CPU BIST data
that could be used not only by SecPlatformInformation2(), but also by CPU MP Dxe
driver to get CPU BIST data.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:36 +08:00
Jeff Fan 8dc56ddeca UefiCpuPkg/CpuMpPei: Fix BistData ouput error
ProcessorInfo.ProcessorId is UINT64 type even it's valid value is UINT32. Use %x
only output the low 4 bytes and keep the high 4 bytes in stack that will be
output as the second parameter BistData. Typecast ProcessorInfo.ProcessorId to
UINT32 could make BistData output correctly.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:32 +08:00
Jeff Fan dfb0e6591b UefiCpuPkg/CpuMpPei: Add parameter BistInformationSize
Add one OPTIONAL parameter BistInformationSize for GetBistInfoFromPpi().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:29 +08:00
Jeff Fan 7d17ab47d1 UefiCpuPkg/CpuDxe: Fix duplicated status code report
If CPU Bist data is not zero, we will report Status code. But there is one bug
that will report each processor's status code duplicated with NumberOfData
times. This fix is to exchange the loop order on NumberOfData and
mNumberOfProcessors. It could make sure the report status code only once for
each processor.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-14 08:54:24 +08:00
Jeff Fan ad8a2f5e68 UefiCpuPkg/XeonPhiMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:18:08 +08:00
Jeff Fan 97ea5b7ff6 UefiCpuPkg/XeonE7Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:18:06 +08:00
Jeff Fan b6ae7578ab UefiCpuPkg/XeonDMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:18:03 +08:00
Jeff Fan eed57645e4 UefiCpuPkg/Xeon5600Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:18:01 +08:00
Jeff Fan 04e7a46528 UefiCpuPkg/SkylakeMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:58 +08:00
Jeff Fan 94fe1b5f53 UefiCpuPkg/SilvermontMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:56 +08:00
Jeff Fan 367f5c9c5f UefiCpuPkg/SandyBridgeMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:53 +08:00
Jeff Fan 634429c0aa UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:50 +08:00
Jeff Fan 65ee84bd6b UefiCpuPkg/PentiumMMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:47 +08:00
Jeff Fan 8bf98bd0d7 UefiCpuPkg/Pentium4Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:45 +08:00
Jeff Fan 91e3003c97 UefiCpuPkg/P6Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:42 +08:00
Jeff Fan c2aa191b50 UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:39 +08:00
Jeff Fan fed6c37b4a UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:35 +08:00
Jeff Fan e108c3f64d UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:32 +08:00
Jeff Fan a73ab08301 UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:28 +08:00
Jeff Fan adf109740f UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:24 +08:00
Jeff Fan e43a671439 UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:20 +08:00
Jeff Fan a6b7bc3c2f UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:16 +08:00
Jeff Fan 800a651d6d UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:13 +08:00
Jeff Fan 7de98828b7 UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in comment
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08 09:17:08 +08:00
Star Zeng b10d5ddc03 UefiCpuPkg/PiSmmCpuDxeSmm: Consume PcdAcpiS3Enable to control the code
if PcdAcpiS3Enable is disabled, then skip S3 related logic.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-09-01 08:18:59 -07:00
Star Zeng 0bdc9e75c0 UefiCpuPkg/PiSmmCpuDxeSmm: Move S3 related code to CpuS3.c
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2016-09-01 08:18:59 -07:00
Star Zeng ca98f60382 UefiCpuPkg/CpuS3DataDxe: Consume PcdAcpiS3Enable to control the code
If PcdAcpiS3Enable is disabled, then return an EFI_UNSUPPORTED
error which forces the module to be unloaded.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-09-01 08:18:59 -07:00
Jeff Fan 3ed4e502b5 UefiCpuPkg/MpInitLib: Don't allocate reset vector in Exit Boot Service
In Exit Boot Services callback function, we cannot use allocate memory services
because it may change the memory map that has been gotten by OS.

This fix is not to allocate reset vector buffer after SaveRestoreFlag is set to
TRUE in MpInitExitBootServicesCallback(). Instead AllocateResetVector() will use
the previous allocated buffer address and save the contents before copying reset
vector code. At the same time, FreeResetVector() will restore original contents
after if SaveRestoreFlag is TRUE.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:55 +08:00
Jeff Fan 42c37b3b33 UefiCpuPkg/MpInitLib: Move two functions location
Just move BackupAndPrepareWakeupBuffer() and RestoreWakeupBuffer() from
PeiMpLib.c to MpLib.c.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:50 +08:00
Jeff Fan b31c1ad11e UefiCpuPkg/MpInitLib: Fix function header comments typo
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:46 +08:00
Jeff Fan d11f10d1e0 UefiCpuPkg/MpInitLib: Rename EndOfPeiFlag to SaveRestoreFlag
It will be used by DxePeiLib also.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:41 +08:00
Jeff Fan 5183fb3736 UefiCpuPkg/MpInitLib: Move allocating reserved memory for AP loop code
In Exit Boot Services callback function, we cannot use allocate memory services
because it may change the memory map that has been gotten by OS.

This fix is to move allocating reserved memory for AP loop code to
InitMpGlobalData() and save the memory address in one global variable.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:37 +08:00
Jeff Fan c119221060 UefiCpuPkg/MpInitLib: Move timeout delay to WakupAp()
After sending the 1st broadcast INIT-SIPI-SIPI, BSP will collect APs count after
one specified timeout delay. However, WakupAp() will restore reset vector
immediately after sending 1st broadcast INIT-SIPI-SIPI. Some processors may not
complete executing reset vector code.

This fix is to move MicroSecondDelay() from CollectProcessorCount() to the place
that is after sending 1st broadcast INIT-SIPI-SIPI and before FreeResetVector()
in WakupAp().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-25 16:12:32 +08:00
Jeff Fan eadf70bdfb UefiCpuPkg/PiSmmCpuDxeSmm: Revert 7503cd70fb
Revert "UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependency"

This reverts commit 7503cd70fb.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
2016-08-19 15:14:28 +08:00
Jeff Fan 8cce3c9a70 UefiCpuPkg/MpInitLib: MicrocodeData used but maybe uninitialized
Cc: Feng Tian <feng.tian@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-19 15:11:01 +08:00
Jeff Fan 7503cd70fb UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependency
PiSmmCpuDxeSmm driver's entry point will get some PCDs supported dynamic type.
In case those PCDs are set as DynamicHii type in platform DSC File, it implies
that EFI Variable Arch protocol is required.

This fix is to add gEfiVariableArchProtocolGuid dependency on PiSmmCpuDxeSmm
driver to make sure those DynamicHii PCDs could be read correctly.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:08:18 +08:00
Jeff Fan f3b91fa04a UefiCpuPkg/CpuDxe: Fixed typo in function header to match PI spec
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:08:01 +08:00
Jeff Fan 0a55f3bd65 UefiCpuPkg/CpuDxe: Remove PcdCpuMaxLogicalProcessorNumber consuming
v5:
  If PcdCpuMaxLogicalProcessorNumber is set to 1 on UP system,
  MpInitLibInitialize() will be invoked. This is one bug, we need to
  call MpInitLibInitialize() always and get the BSP information.
  Just to remove PcdCpuMaxLogicalProcessorNumber() consuming from this
  driver.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:07:16 +08:00
Jeff Fan 39d49a73a5 UefiCpuPkg/CpuDxe: Remove unused codes and files
v5:
  1. Remove unused PcdCpuApStackSize and PcdCpuApInitTimeOutInMicroSeconds.

v4:
  1. Keep GDT table setup to fix IA32 S3 boot issue.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:07:07 +08:00
Jeff Fan 0b9f0dd635 UefiCpuPkg/CpuDxe: Move SetMtrrsFromBuffer() location.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:07:00 +08:00
Jeff Fan 7fadaacd50 UefiCpuPkg/CpuDxe: Consume MpInitLib to produce CPU MP Protocol services
Consume MP Initialize library to produce CPU MP Protocol services to simply the
code.

v4:
  1. Update CpuDxe.c file header to mention it produces CPU Arch protocol.
  2. Update BistData type from UINT32 to EFI_HEALTH_FLAG.
  3. Move some header location from CpuMp.h to CpuDxe.h.

v3:
  1. Move the code Consume MpInitLib APIs to produce CPU MP Protocol from patch
     #40 to this patch.
  2. Add DxeMpInitLib.inf in DSC file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:56 +08:00
Jeff Fan 89fa1bf218 UefiCpuPkg/CpuMpPei: Delete PeiMpServices.c and PeiMpServices.h
Move the code in PeiMpServices.c & PeiMpServices.h to CpuMpPei.c & CpuMpPei.h.

v3:
  1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP
  2. Add PeiMpInitLib.inf in DSC file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:51 +08:00
Jeff Fan 4b0eeef313 UefiCpuPkg/CpuMpPei: Remove unused files and codes
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:43 +08:00
Jeff Fan a1a4c7a467 UefiCpuPkg/CpuMpPei: Consume MpInitLib to produce CPU MP PPI services
Consume MP initialize library to produce CPU MP PPI, it could simply the code.

Add STATIC for some internal functions to avoid build issue with the same
functions name in PeiMpInit instance. They will be removed by the next patch.

v4:
  1. Update BistData type from UINT32 to EFI_HEALTH_FLAGS.

v3:
  1. Rename MpInitLibSwitchBSP to MpInitLibSwitchBSP
  2. Add PeiMpInitLib.inf in DSC file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:06:30 +08:00
Jeff Fan 4d3314f694 UefiCpuPkg/MpInitLib: Place APs in safe loop before hand-off to OS
Register Exit Boot Service callback function MpInitExitBootServicesCallback() to
place AP one safe loop before hand-off to OS.

Allocated one reserved memory and copy the AsmRellocateApLoop() code into it. It
could avoid the CPU Dxe driver (located in Boot Service data range) crashed
after Exit Boot Service event.
Place AP into the target Cx-State (specified by PcdCpuApTargetCstate) could save
power if Monitor-mwait feature supported.
In long mode, switch AP into protected mode could let AP not require page table
when executing this safe loop. Page Table (located in Boot Service data range)
may crashed after Exit Boot Service event.

v3:
  1. Rename *RellocateAp* to *RelocateAp*

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:39 +08:00
Jeff Fan 86efe97693 UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupAllAPs()
v4:
  1. Simply the internal function StartupAllAPsWorker()'s function
     header due to it is duplicated with MpInitLibStartupAllAPs().
v3:
  1. Use CamelCase for mStopCheckAllApsStatus and
     CheckAndUpdateApsStatus()

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:31 +08:00
Jeff Fan 20ae57745b UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupThisAP()
v4:
  1. Simply the internal function StartupThisAPWorker()'s comment
     header due to it is duplicated with MpInitLibStartupThisAP().

v3:
  1. Use CamelCase for mStopCheckAllApsStatus and
     CheckAndUpdateApsStatus().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:26 +08:00
Jeff Fan 08085f08ec UefiCpuPkg/MpInitLib: Check APs Status and update APs status
v3:
  1. Use CamelCase for CheckAndUpdateApsStatus().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:22 +08:00
Jeff Fan e37109bcc7 UefiCpuPkg/MpInitLib: Implementation of MpInitLibEnableDisableAP()
v4:
  1. Simply the internal function MpInitLibEnableDisableAP()'s function
     header due to it is duplicated with MpInitLibEnableDisableAP().
v3:
  1. Use CamelCase for mCheckAllAPsEvent, mStopCheckAllApsStatus.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:17 +08:00
Jeff Fan 41be0da59a UefiCpuPkg/MpInitLib: Implementation of MpInitLibSwitchBSP()
v4:
  1. Simply the internal function SwitchBSPWorker()'s comment header
     due to it is duplicated with MpInitLibSwitchBSP().

v3:
  1. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:13 +08:00
Jeff Fan 5c9e099797 UefiCpuPkg/MpInitLib: Implementation of MpInitLibWhoAmI()
v5:
  1. Move checking ProcessNumber before calling GetCpuMpData.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:09 +08:00
Jeff Fan ad52f25edf UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetProcessorInfo()
v5:
  1. Remove (-1) and use the clean code to calculate the Location->Thread
     and Location->Core.

v4:
  1. Update HealthData type from UINT32 to EFI_HEALTH_FLAGS

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:02:05 +08:00
Jeff Fan 809213a679 UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetNumberOfProcessors()
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:59 +08:00
Jeff Fan 6a2ee2bb63 UefiCpuPkg/MpInitLib: Skip collect processor count if GUIDed HOB exist
If GUIDed HOB mCpuInitMpLibHobGuid exists, we could get the processor count and
processor APICID and Initial APICID from CPU_INFO_IN_HOB. We needn't to delay
for broadcast INIT-SIPI-SIPI results and could improve performance.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:55 +08:00
Jeff Fan 8a2d564b2a UefiCpuPkg/MpInitLib: Sort processor by ascending order of APIC ID
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:49 +08:00
Jeff Fan fe627769c9 UefiCpuPkg/MpInitLib: Enable x2APIC mode on BSP/APs
If x2APIC flag is set, enable x2APIC mode on all APs and BSP. Before we wakeup
APs to enable x2APIC mode, we should wait all APs have finished initialization.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:45 +08:00
Jeff Fan 03434dffb7 UefiCpuPkg/MpInitLib: Send INIT-SIPI-SIPI to get processor count
CollectProcessorCount() will send the 1st INIT-SIPI-SIPI to get processor count
in system.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:40 +08:00
Jeff Fan 96f5920d1d UefiCpuPkg/MpInitLib: Add WakeUpAP()
WakeUpAP() is used to wakeup APs per current ApLoopMode and make sure APs wake
up successfully.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:04 +08:00
Jeff Fan 7c3f2a1253 UefiCpuPkg/MpInitLib: Fill MP_CPU_EXCHANGE_INFO fields
FillExchangeInfoData() is used to fill MP_CPU_EXCHANGE_INFO date exchanged
between C code and assembly code of AP reset vector.

v5:
  1. Reference ApWakeupFunction instead of ApCFunction.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:01:00 +08:00
Jeff Fan b8b04307eb UefiCpuPkg/MpInitLib: Add ApWakeupFunction() executed by assembly code
ApWakeupFunction() is the first C function executed from AP reset vector. When
APs waken up at the first time, it will sync BSP's MTRR setting and load
microcode on APs and collect APs' BIST information.

When AP tasked finished, it will place APs it one loop specified by ApLoopMode.

v5:
  1. Rename ApCFunction to ApWakeupFunction to meet naming convention.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:54 +08:00
Jeff Fan ed66e0e3f4 UefiCpuPkg/MpInitLib: Allocate AP reset vector buffer under 1MB
In PeiMpInitLib, searching unallocated memory under in
EFI_HOB_TYPE_RESOURCE_DESCRIPTOR hobs to find the memory under 1MB for AP reset
vector. After End of PEI event triggered, we need to restore original the buffer
contents to avoid crash the OS on S3 boot.
In DxeMpInitLib, allocate the memory under 1MB for AP reset vector.

Add helper functions AllocateResetVector()/FreeResetVector() used by WakeupAp().

v3:
  1. Move SetTimer() from Patch #17 to Patch 16.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:50 +08:00
Jeff Fan 963788618b UefiCpuPkg/MpInitLib: Register one period event to check APs status
In DxeMpInitLib, register one period event callback function CheckAPsStatus()
used to check AP Status.

v5:
  1. Introduce AP_CHECK_INTERVAL for adjust AP check timer interval potential.

v3:
  1. Use CamelCase for mCheckAllAPsEvent, mStopCheckAllApsStatus and
     CheckAndUpdateApsStatus().
  2. Move SetTimer() from Patch #17 to Patch 16.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:44 +08:00
Jeff Fan 6dc05093a0 UefiCpuPkg/MpInitLib: Register one End of PEI callback function
In PeiMpInitLib, register End of PEI callback function CpuMpEndOfPeiCallback().

v5:
  1. Add comment block for mMpInitLibNotifyList.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:32 +08:00
Jeff Fan 93ca4c0fd7 UefiCpuPkg/MpInitLib: Save CPU MP Data pointer
In PeiMpInitLib, save CPU MP Data pointer into one local Guided HOB.
In DxeMpInitLib, save CPU MP Data pointer into one global variable.

Add helper functions GetCpuMpData()/SaveCpuMpData().

v5:
  1. Move CPU_INIT_MP_LIB_HOB_GUID from MpLib.c to MpLib.h to make
     all C files visible.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:28 +08:00
Jeff Fan 94f63c765f UefiCpuPkg/MpInitLib: Add MicrocodeDetect() and load microcode on BSP
v4:
  1. ProcessorSignature is updated to CPU_MICROCODE_PROCESSOR_SIGNATURE
     instead of UINT32.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:23 +08:00
Jeff Fan 68cb933071 UefiCpuPkg/MpInitLib: Add CPU_VOLATILE_REGISTERS & worker functions
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored
after APs received INIT IPI.

Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to
save/restore CRx and DRx. It also check if Debugging Extensions supported or
not.

v5:
  1. Add comment block for structure CPU_VOLATILE_REGISTERS.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:19 +08:00
Jeff Fan 03a1a92515 UefiCpuPkg/MpInitLib: Initialize CPU_AP_DATA for CPU APs
Initialize CPU_AP_DATA for CPU APs and add GetApState()/SetApState() helper
functions to get/set AP state.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 20:00:15 +08:00
Jeff Fan e59f8f6b36 UefiCpuPkg/MpInitLib: Allocate and initialize memory of MP Data buffer
v5:
  1. Add comment block for enum AP_INIT_STATE and structure CPU_AP_DATA.
  2. Add more comment for structure CPU_INFO_IN_HOB.
  3. Add more clarification in structure _CPU_MP_DATA for those fields
     pass from PEI to DXE.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:59:12 +08:00
Jeff Fan 9ebcf0f400 UefiCpuPkg/MpInitLib: Get ApLoopMode and MointorFilter size
Firstly, get ApLoopMode from PcdCpuApLoopMode. If MonitorMwait feature is not
supported, update ApLoopMode to ApHltLoop. If MonitorMwait feature is supported,
get MointorFilter size by CPUID.[EAX=05H]:EBX.BIT0-15.

v5:
  1. Add comment block for enum AP_LOOP_MODE.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:59:06 +08:00
Jeff Fan f7f85d8360 UefiCpuPkg/MpInitLib: Add MP_ASSEMBLY_ADDRESS_MAP
In MpInitLibInitialize(), invoke AsmGetAddress() to get get assembly functions'
entry addresses and the sizes from returned MP_ASSEMBLY_ADDRESS_MAP structure.

v5:
  1. Add more detailed comments for structure MP_ASSEMBLY_ADDRESS_MAP.

v4:
  1. Add AsmRelocateApLoop information return in AsmGetAddress().

v3:
  1. Rename AsmRellocateApLoop to AsmRelocateApLoop.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:59:01 +08:00
Jeff Fan 7615702169 UefiCpuPkg/MpInitLib: Add AsmRelocateApLoop() assembly code
AsmRelocateApLoop() is used to place APs into MWAIT-loop if MonitorMwait
feature is supported before hand-off to OS, or place APs into HLT-loop if
MonitorMwait feature is not supported.

If the current mode is long mode, we will switch APs to protected mode
before placing APs in MWAIT-loop or HLT-loop. Thus, once APs wakeup from
loop, APs needn't the page table that may be crashed by OS.

v3:
  1. Rename AsmRellocateApLoop to AsmRelocateApLoop.
  2. Fix typo Proteced to Protected.
  3. Fix typo segement to segment
  4. Use word MONITOR instead of mwait-monitor.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:56 +08:00
Jeff Fan 5c66d125ea UefiCpuPkg/MpInitLib: Add EnableExecuteDisable in MP_CPU_EXCHANGE_INFO
EnableExecuteDisable in MP_CPU_EXCHANGE_INFO is used to tell AP reset vector if
enable execute disable feature on APs. This feature should be enabled before CR3
is written.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:48 +08:00
Jeff Fan 8396e2dd30 UefiCpuPkg/MpInitLib: Fix typo and clean up the code
1. Rename NumApsExecutingLoction to NumApsExecutingLocation
2. Update some comments in NASM files.
3. Remove PeiCpuMpData from MP_CPU_EXCHANGE_INFO.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:37 +08:00
Jeff Fan d94e5f6729 UefiCpuPkg/MpInitLib: Add AP assembly code and MP_CPU_EXCHANGE_INFO
Add assembly code for AP reset vector and the definition of MP_CPU_EXCHANGE_INFO
that are used to exchange the data between C code and assembly code when AP wake
up.

v4:
  1. Copy MP_CPU_EXCHANGE_INFO from UefiCpuPkg/CpuMpPei/CpuMpPei.h
  2. Copy MpEqu.inc and MpFuncs.nasm from UefiCpuPkg/CpuMpPei.

v3:
  1. Rename NumApsExecutingLoction to NumApsExecutingLocation
  2. Add whitespace after ; in .nasm file

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:30 +08:00
Jeff Fan 3e8ad6bd76 UefiCpuPkg/MpInitLib: Add two instances PeiMpInitLib and DxeMpInitLib
Add two MP Initialize Library instances PeiMpInitLib.inf and DxeMpInitLib.inf
with NULL implementation.

One PeiMpInitLib.inf is consumed by PEI MP driver. Another DxeMpInitLib.inf is
consumed by DXE MP driver.

Place MpInitLibStartupAllAPs()/MpInitLibStartupThisAp()/MpInitLibSwitchBSP()/
MpInitLibEnableDisableAP() into PeiMpLib.c and DxeMpLib.c, because they have
the different implementations and will be updated in latter patches.

v5:
  1. Add back PeiExceptionHandlerLib.inf in UefiCpuPkg.dsc. It is removed
     incorrectly.

v4:
  1. Return EFI_UNSUPPORTED instead of EFI_SUCCESS for NULL implementation of
     all Functions.
  2. Sync MpInitLibxxx functions header updating described in v4 part of Patch
     #4.

v3:
  1. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:58:07 +08:00
Jeff Fan 87896d03f6 UefiCpuPkg/MpInitLib: Add MP Initialize library class definition
MP Initialize library provides basic functionalities to do APs initialization,
to manage MP information and to wakeup APs to execute AP task.

It could be consumed by CPU MP PEI or DXE drivers to provide CPU MP PPI/Protocol
services.

v4:
  1. MpInitLibGetProcessorInfo():
     Update HealthData type from UINT32 to EFI_HEALTH_FLAGS.
     Add #include <Ppi/SecPlatformInformation.h>
  2. MpInitLibSwitchBSP():
     Return EFI_DEVICE_ERROR instead of EFI_SUCCESS if the calling processor is
     an AP.
  3. MpInitLibStartupThisAP():
     Fix several incorrect references to "APs" to match PI spec.
  4. MpInitLibSwitchBSP() and MpInitLibEnableDisableAP():
     Fix incorrect description on ProcessorNumber.
  5. Trim whitespace at end of line.

v3:
  1. Add whitespace after MpInitLibInitialize
  2. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:57:41 +08:00
Jeff Fan 65b24ada79 UefiCpuPkg/CpuS3DataDxe: Move StartupVector allocation to EndOfDxe()
Currently, we will allocate StartupVector buffer under 1MB at entry point
function. But some modules may allocate some hard code address under 1MB.
For example, LegacyBiosDxe driver tries to manage some legacy range under
640KB.

To avoid the conflicts, we move StartupVector buffer allocation to End Of
DXE event callback function.

v4:
  Update the Context parameter is used as a pointer to AcpiCpuDataEx, then
  we needn't to add the global variable.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:57:32 +08:00
Jeff Fan 5aa2d57667 UefiCpuPkg/MpInitLib: Add microcode definitions defined in IA32 SDM
Add microcode definitions defined in Intel(R) 64 and IA-32 Architectures
Software Developer's Manual Volume 3A, Section 9.11.

v4:
  1. ProcessorSignature type changed to CPU_MICROCODE_PROCESSOR_SIGNATURE
  2. Add pack(1) for structure CPU_MICROCODE_HEADER and
     CPU_MICROCODE_EXTENDED_TABLE.
v3:
  1. Update SDM date to June, 2016
  2. Mention BCD format in CPU_MICROCODE_DATE
  3. Rename ProcessorChecksum to Checksum to match SDM.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:55:25 +08:00
Jeff Fan a742e1865d UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions
#define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.

Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
ArchitecturalMsr.h.

v5:
  1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17 19:54:41 +08:00
Ruiyu Ni 490b048b5a UefiCpuPkg: MTRR_PHYSMASK.Valid should be one bit instead of 8 bits
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-08-17 13:54:13 +08:00
Hao Wu 72a8abde40 UefiCpuPkg DSC: Add build option to disable deprecated APIs
Add the following definition in the [BuildOptions] section in package DSC
files to disable APIs that are deprecated:

[BuildOptions]
  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-08-08 11:00:12 +08:00
Jeff Fan e78a2a49ee UefiCpuPkg/PiSmmCpuDxeSmm: SMM_CPU_DATA_BLOCK is not cleared
The commit 8b9311 changed the zeroing of mSmmMpSyncData of type
SMM_DISPATCHER_MP_SYNC_DATA by the following patch.
 -    ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize);
 +    mSmmMpSyncData->SwitchBsp = FALSE;

mSmmMpSyncDataSize not only includes SMM_DISPATCHER_MP_SYNC_DATA, but
also includes the SMM_CPU_DATA_BLOCK array and one BOOLEAN variable
array as shown here:

  mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) +
       (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) *
       gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;

This patch restores the original ZeroMem() to clear all CPU Sync data.
The commit 8b9311 may cause unexpected behavior.

v2:
  Mentioned CandidateBsp array in comments to make it more accurate.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-07-20 18:50:53 -07:00
Jeff Fan afa7b97154 UefiCpuPkg/CpuDxe: StartupAllAPs in parallel mode
SetMemoryAttributes() will sync BSP's MTRRs settings to all APs by StartupAllAPs
service in serial mode. It may caused much performance impact if there are too
much processors in system. This update is to invoke StartupAllAps in parallel
mode. IA32 SDM does suggest to program MTRRs in parallel mode.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-07-20 11:13:25 +08:00
Jeff Fan 81f560498b UefiCpuPkg/MtrrLib: Add notes for usage by BSP/APs
Except for MtrrSetAllMtrrs(), others services are not suggested to be invoked by
APs because they are not necessary and may invoke DEBUG() to dump MTRR setting.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed: Laszlo Ersek <lersek@redhat.com>
2016-07-20 11:13:02 +08:00
Jeff Fan 9fc34794d6 UefiCpuPkg/MtrrLib: Remove MTRRs display from MtrrSetAllMtrrs()
MtrrSetAllMtrrs() maybe used by APs to sync BSP's MTRR settings. BSP's MTRR
setting should be displayed if EFI_D_CACHE flag is set when MTRR updated. In
MtrrSetAllMtrrs(), it's not necessary to display MTRR setting again due to the
MTRR settings should be always same among BSP/APs. This updating could avoid
APs output MTRR setting at the same time and make display message corrupted.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-07-20 11:12:20 +08:00
Laszlo Ersek 09a85f6eeb UefiCpuPkg/PiSmmCpuDxeSmm: remove superfluous ENDs from NASM source
Commits 28ee581646 and 246cd9085f added these ENDs as part of the
manual conversion from *.asm files. However, the ENDs makes no sense for
NASM. Although they don't break the build, NASM complains about them:

  label alone on a line without a colon might be in error

(This NASM warning category dates back to NASM 0.95, commit
6768eb71d8deb.)

Remove the ENDs.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-07-18 19:23:01 +02:00
Jeff Fan 51773d49de UefiCpuPkg/PiSmmCpuDxeSmm: Clean up CheckFeatureSupported()
Removed EFIAPI and parameter from CheckFeatureSupported() and removed
CheckProcessorFeature() totally.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:58:04 -07:00
Jeff Fan a46a4c90d3 UefiCpuPkg/PiSmmCpuDxeSmm: Check XD/BTS features in SMM relocation
CheckProcessorFeature() invokes MpService->StartupAllAps() to detect
XD/BTS features on normal boot path. It's not necessary and may cause
performance impact, because INIT-SIPI-SIPI must be sent to APs if APs
are in hlt-loop mode. XD/BTS feature detection is moved to
SmmInitHandler() in SMM relocation during normal boot path.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:59 -07:00
Jeff Fan 70a7493d65 UefiCpuPkg/PiSmmCpuDxeSmm: Add SMM S3 boot flag
It will be set to TRUE during S3 resume.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:53 -07:00
Jeff Fan 6c4c15fae6 UefiCpuPkg/PiSmmCpuDxeSmm: Add MemoryMapped in SetProcessorRegister()
REGISTER_TYPE in UefiCpuPkg/Include/AcpiCpuData.h defines a MemoryMapped
enum value.  However support for the MemoryMapped enum is missing from
the implementation of SetProcessorRegister().  This patch adds support
for MemoryMapped type SetProcessorRegister().

One spin lock is added to avoid potential conflict when multiple processor
update the same memory space.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:47 -07:00
Jeff Fan 8b9311b795 UefiCpuPkg/PiSmmCpuDxeSmm: Remove duplicate aligned buffer on S3 path
InitializeMpSyncData() invokes InitializeSmmCpuSemaphores() to allocate an
aligned buffer for all locks and semaphores. However, this function is
invoked on S3 resume path again to reset mSmmMpSyncData. It causes
an additional aligned buffer to be allocated.

This update moves InitializeSmmCpuSemaphores() into
InitializeMpServiceData() that is only invoked on normal boot.
InitializeMpSyncData() is updated to reset the locks/semaphore in
mSmmMpSyncData.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-07-14 08:57:41 -07:00
Jeff Fan 01beffa7e9 UefiCpuPkg/CpuMpPei: Remove PmodeOffset and LmodeOffset
Remove Pmode(Entry)Offset/Lmode(Entry)Offset and use unified Mode(Entry)Offset
to clean up the definition of MP_ASSEMBLY_ADDRESS_MAP and MP_CPU_EXCHANGE_INFO.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:44:09 +08:00
Jeff Fan 6d98a37159 UefiCpuPkg/CpuMpPei: Remove un-used variables and functions
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:44:04 +08:00
Jeff Fan 9c3d2f9a29 UefiCpuPkg/CpuMpPei: Do not load new GDT table
Do not load the new GDT table and just to use the exiting BSP's GDT table set up
by SEC phase.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:44:00 +08:00
Jeff Fan d1471c0112 UefiCpuPkg/CpuMpPei/X64: Use CodeSegment and DataSegment fields
Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode
MACROs for x64 arch. Switch AP from real mode to long mode directly, so needn't
the CS/DS of protected mode.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:43:36 +08:00
Jeff Fan 249ed12ea0 UefiCpuPkg/CpuMpPei/X64: Remove hard code CPU BIST value
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:41:44 +08:00
Jeff Fan aad5ee4899 UefiCpuPkg/CpuMpPei/Ia32: Use CodeSegment and DataSegment fields
Using CodeSegment and DataSegment fields in ExchangeInfo instead of the hardcode
MACROs.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:41:20 +08:00
Jeff Fan ed04bffe75 UefiCpuPkg/CpuMpPei: Add CodeSegment and DataSegment fields
Added CodeSegment and DataSegment fields in MP_CPU_EXCHANGE_INFO. They are set
to the values of current BSP's CS and DS.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Giri Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-14 09:33:24 +08:00
Jeff Fan 30dc4a49b6 UefiCpuPkg/CpuMpPei: Remove unnecessary variable
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-13 15:42:10 +08:00
Jeff Fan 719ff8cf3e UefiCpuPkg/CpuMpPei: Dump message if microcode signature not matched
Verification microcode signature is one enhancement and not one requirement from
IA32 SDM. This update is just to dump debug message instead of ASSERT() if the
updated microcode signature does not match the loaded microcode signature.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-13 15:41:49 +08:00
Jeff Fan 46fd118219 UefiCpuPkg/CpuMpPei: Skip microcode check/load if it has been loaded
Actually, there is only one microcode region in platform. If microcode has been
loaded, its signature will not be zero and should be loaded successfully.
We needn't to check microcode region and load microcode again. This update is to
skip checking/loading microcode if current microcode signature is not zero.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-07-13 15:41:14 +08:00
Liming Gao 6f5531d504 UefiCpuPkg CpuMpPei: Update INF to refer to NASM source file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:22 +08:00
Liming Gao 68d37176a5 UefiCpuPkg CpuIo2Dxe: Update INF to refer to NASM source file
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:22 +08:00
Liming Gao 9caff8d961 UefiCpuPkg SecCore: Update SecCore inf to refer to nasmb source
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 13:20:21 +08:00
Giri P Mudusuru 8ed9ce80a6 UefiCpuPkg: Fix typos in comments
- becasue to because

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-11 10:29:51 +08:00
Star Zeng 6f9760d88b UefiCpuPkg S3Resume2Pei: Report status code when allocate memory is failed
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-07-02 12:22:55 +08:00
Laszlo Ersek ef3e20e3ca UefiCpuPkg: fix ASSERT_EFI_ERROR() typos
A number of code locations use

  ASSERT_EFI_ERROR (BooleanExpression)

instead of

  ASSERT (BooleanExpression)

Fix them.

Cc: Jeff Fan <jeff.fan@intel.com>
Reported-by: Gerd Hoffmann <kraxel@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-06-30 17:27:38 +02:00
Liming Gao ad9ec7efad UefiCpuPkg PiSmmCpuDxeSmm: Add nasm source file into INF file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:19 +08:00
Liming Gao ba15b97142 UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmmInit.asm to NASM
Manually convert X64/SmmInit.asm to X64/SmmInit.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:18 +08:00
Liming Gao 9f54832f4b UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiException.asm to NASM
Manually convert X64/SmiException.asm to X64/SmiException.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:18 +08:00
Liming Gao 9a36d4dc3f UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/SmiEntry.asm to NASM
Manually convert X64/SmiEntry.asm to X64/SmiEntry.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:17 +08:00
Liming Gao e1f0eed1b2 UefiCpuPkg PiSmmCpuDxeSmm: Update X64/MpFuncs.nasm
Use 16bit and 32bit assembly code to replace hard code db.

In V2: add 0x67 prefixes to far jumps

Without the a32 modifier under FLAT32_JUMP, and the a16 modifier under
LONG_JUMP, nasm doesn't generate the 0x67 prefixes, and the far jumps
don't work. (For the former, KVM returns an emulation failure. For the
latter, KVM performs a triple fault (guest reboot).) By forcing the 0x67
prefixes we end up with the same machine code as the one open-coded in
"MpFuncs.asm".

This bug breaks S3 resume in the Ia32X64 + SMM_REQUIRE build of OVMF.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-06-28 09:52:16 +08:00
Liming Gao 78cf66eebb UefiCpuPkg PiSmmCpuDxeSmm: Convert X64/MpFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/MpFuncs.asm to X64/MpFuncs.nasm
And, manually update it to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:16 +08:00
Liming Gao 246cd9085f UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmmInit.asm to NASM
Manually convert Ia32/SmmInit.asm to Ia32/SmmInit.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:15 +08:00
Liming Gao 28ee581646 UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiException.asm to NASM
Manually convert Ia32/SmiException.asm to Ia32/SmiException.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:15 +08:00
Liming Gao 63a4f46076 UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/SmiEntry.asm to NASM
Manually convert Ia32/SmiEntry.asm to Ia32/SmiEntry.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:14 +08:00
Liming Gao 55c6d5467e UefiCpuPkg PiSmmCpuDxeSmm: Update Ia32/MpFuncs.nasm
Use 16bit assembly code to replace hard code db.

In V2:
Add 0x67 prefix to far jump

When we enter protected mode, with the far jump still in big real mode,
the JMP instruction not only needs the 0x66 prefix (for 32-bit operand
size), but also the 0x67 prefix (for 32-bit address size). Use the a32
nasm modifier to enforce this.

This bug breaks S3 resume in the Ia32 + SMM_REQUIRE build of OVMF.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-06-28 09:52:13 +08:00
Liming Gao 6997711e7f UefiCpuPkg PiSmmCpuDxeSmm: Convert Ia32/MpFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/MpFuncs.asm to Ia32/MpFuncs.nasm.
And, manually update it to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:13 +08:00
Liming Gao ac6229a7b8 UefiCpuPkg S3Resume2Pei: Add nasm source file into INF file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:12 +08:00
Liming Gao b3cfdef49e UefiCpuPkg S3Resume2Pei: Convert X64/AsmFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/AsmFuncs.asm to X64/AsmFuncs.nasm.
And, manually add o16 prefix to specify 16bit operation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:12 +08:00
Liming Gao 5104be5fcf UefiCpuPkg S3Resume2Pei: Convert Ia32/AsmFuncs.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/AsmFuncs.asm to Ia32/AsmFuncs.nasm.
And, manually add o16 prefix to specify 16bit operation.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:11 +08:00
Liming Gao 70f3acf98a UefiCpuPkg CpuExceptionHandlerLib: Add nasm source files into INF files.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:10 +08:00
Liming Gao fb501e33c3 UefiCpuPkg CpuExceptionHandlerLib:Convert X64/ExceptionHandlerAsm.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/ExceptionHandlerAsm.asm to X64/ExceptionHandlerAsm.nasm.
Then, manually update nasm to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:10 +08:00
Liming Gao ab7efb664c UefiCpuPkg CpuExceptionHandlerLib:Convert Ia32/ExceptionHandlerAsm.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/ExceptionHandlerAsm.asm to Ia32/ExceptionHandlerAsm.nasm.
Then, manually update nasm to pass build.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:09 +08:00
Liming Gao 6bfe841ff2 UefiCpuPkg BaseUefiCpuLib: Add nasm source file in BaseUefiCpuLib.inf
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:08 +08:00
Liming Gao ce3e0a906f UefiCpuPkg BaseUefiCpuLib: Convert X64/InitializeFpu.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
X64/InitializeFpu.asm to X64/InitializeFpu.nasm.
And, manually add .rdata section.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:08 +08:00
Liming Gao f893042d05 UefiCpuPkg BaseUefiCpuLib: Convert Ia32/InitializeFpu.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/InitializeFpu.asm to Ia32/InitializeFpu.nasm.
And, manually add .rdata section.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:07 +08:00
Liming Gao b85a6ffb44 UefiCpuPkg CpuDxe: Add nasm source file in CpuDxe.inf
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:06 +08:00
Liming Gao 762e073a93 UefiCpuPkg CpuDxe: Convert Ia32/CpuAsm.asm to NASM
The BaseTools/Scripts/ConvertMasmToNasm.py script was used to convert
Ia32/CpuAsm.asm to Ia32/CpuAsm.nasm

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
2016-06-28 09:52:06 +08:00
Marvin H?user 61257251b2 UefiCpuPkg/SecMain: Decorate phase-transition function with NORETURN.
This patch adds the NORETURN attribute to the function that transfers
to the PEI phase, along with an UNREACHABLE() call at the end to
avoid false warnings.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-06-22 09:37:22 +08:00
Jeff Fan eecad34987 UefiCpuPkg/MtrrLib: Fixed bug if length is less than Fixed-MTRR range
Currently, if the memory length to be programmed is less than the remaining size
of one Fixed-MTRR supported, RETURN_UNSUPPORTED returned. This is not correct.
This is one regression at 07e8892090 when we
updated ProgramFixedMtrr() to remove the loop of calculating Fixed-MTRR Mask.

This fix will calculate Right offset in Fixed-MTRR beside left offset. It
supports small length (less than remaining size supported by Fixed-MTRR) to be
programmed.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-06-07 13:09:25 +08:00
Laszlo Ersek 509f8425b7 UefiCpuPkg: change PcdCpuSmmStackGuard default to TRUE
This Feature PCD causes PiSmmCpuDxe to catch SMM stack overflow at
runtime, logging a clear error message, and entering a CPU dead loop.
Compared to the chaotic and catastrophic consequences of the stack leaking
into, and corrupting, the SMM page table, a stack guard that is enabled by
default is vastly superior.

We should not require sane platforms to explicitly opt in to this
safeguard; instead, we should require platforms that prefer to live
dangerously to opt out of it.

Stack overflow in SMM might even give rise to security vulnerabilities.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/12864
Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1341733
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-06-06 10:58:24 +02:00
Jeff Fan 9bedfb2f5b UefiCpuPkg/CpuMpPei: Consume CpuExceptionHandlerLib
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:37:01 +08:00
Jeff Fan a81abf1616 UefiCpuPkg/ExceptionLib: Import PeiCpuExceptionHandlerLib module
This module could be linked by CpuMpPei driver to handle reserved vector list
and provide spin lock for BSP/APs to prevent dump message corrupted.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:36:14 +08:00
Jeff Fan d91225cfad UefiCpuPkg/ExceptionLib: Move global variable location
Move some global variables location from PeiDxeSmmCpuException.c to
DxeCpuException.c and SmmCpuException.c. And remove some un-used global
vairables.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:58 +08:00
Jeff Fan 44ecbc28b6 UefiCpuPkg/ExceptionLib: Add CommonExceptionHandlerWorker()
Add internal worker function RegisterCpuInterruptHandlerWorker().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:53 +08:00
Jeff Fan 670f13af60 UefiCpuPkg/ExceptionLib: Update RegisterCpuInterruptHandlerWorker()
Add parameter CpuExceptionData for RegisterCpuInterruptHandlerWorker().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:48 +08:00
Jeff Fan 9db15f8148 UefiCpuPkg/ExceptionLib: Update UpdateIdtTable()
Add parameter CpuExceptionData for UpdateIdtTable().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:44 +08:00
Jeff Fan ab95e54dc4 UefiCpuPkg/ExceptionLib: Update InitializeCpuExceptionHandlersWorker
Add parameter CpuExceptionData for InitializeCpuExceptionHandlersWorker().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:40 +08:00
Jeff Fan 2c5873fede UefiCpuPkg/ExceptionLib: Add EXCEPTION_HANDLER_DATA definition
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:31:36 +08:00
Jeff Fan 9b4aa7602e UefiCpuPkg/ExceptionLib: Rename DxeSmmCpuException.c
Rename DxeSmmCpuException.c to PeiDxeSmmCpuException.c that will be used by
PeiCpuExceptionHandlerLib.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-06-01 15:30:38 +08:00
Jeff Fan dc99315b87 UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned buffer
Update MSRs semaphores to the ones in allocated aligned semaphores
buffer. If MSRs semaphores is not enough, allocate one page more.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:22 -07:00
Jeff Fan 695e62d141 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphores
Allocate MSRs semaphores in allocated aligned semaphores buffer.
And add it into semaphores structure.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:17 -07:00
Jeff Fan ed3d5ecb34 UefiCpuPkg/PiSmmCpuDxeSmm: Using CPU semaphores in aligned buffer
Update each CPU semaphores to the ones in allocated aligned
semaphores buffer.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:12 -07:00
Jeff Fan 4e92058113 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for each CPU semaphores
Allocate each CPU semaphores in allocated aligned semaphores buffer.
And add it into semaphores structure.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:07 -07:00
Jeff Fan fe3a75bc41 UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned buffer
Update all global semaphores to the ones in allocated aligned
semaphores buffer.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:20:01 -07:00
Jeff Fan d67b73cc38 UefiCpuPkg/PiSmmCpuDxeSmm: Move forward MP sync data initialization
Move MP sync data initialization in front of the place that initialize
page table, because the page fault spin lock is allocated in
InitializeMpSyncData() while it is initialized in SmmInitPageTable().

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:19:55 -07:00
Jeff Fan 1d64853193 UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for global semaphores
Get semaphores alignment/size requirement and allocate aligned
buffer for all global spin lock and semaphores.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24 15:19:47 -07:00
Michael Kinney 728de7a073 UefiCpuPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields check
SMRR range size and alignment should follow the rules like MTRR:
a. The minimum range size is 4 KBytes and the base address of the
   range must be on at least a 4-KByte boundary.
b. For ranges greater than 4 KBytes, each range must be of length
   2^n and its base address must be aligned on a 2^n boundary, where
   n is a value equal to or greater than 12. The base-address
   alignment value cannot be less than its length.
Thus, it could meet "Address_Within_Range AND PhysMask = PhysBase
AND PhysMask".

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
2016-05-19 10:04:27 -07:00
Jeff Fan f85d3ce2ef UefiCpuPkg/PiSmmCpuDxeSmm: Use public MSR_IA32_MISC_ENABLE definition
Use the MSR MSR_IA32_MISC_ENABLE definition defined in UefiCpuPkg/Include and
remove the local definition.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16 10:40:19 -07:00
Jeff Fan 846704334c UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Remove unnecessary BTS MSRs
BTS used DS save area by IA32_DS_AREA MSR to get invoker IP instead of the
Last Branch Record Stack. So, removed the unnecessary BTS MSRs.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16 10:40:18 -07:00
Jeff Fan 4b1f9ac19d UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Fix BTS support check bug
SmmProfile feature depends on BTS feature to get the invoker IP (in SMM) from
last branch record. If this feature is not supported, SmmProfile cannot get the
invoker IP (in SMM). Per IA-32 Architectures Software Developer's Manual, BTS
feature is detected by IA32_MISC_ENABLE. If BIT11 of IA32_MISC_ENABLE is set,
BTS is not supported. But current implementation check BIT11 opposite. Also, BTS
feature does not depends on PEBS feature if supported or not.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Shifflett, Joseph <joseph.shifflett@hpe.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reported-by: Shifflett, Joseph <joseph.shifflett@hpe.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Shifflett, Joseph <joseph.shifflett@hpe.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16 10:40:16 -07:00
Jeff Fan 07e8892090 UefiCpuPkg/MtrrLib: Remove the loop of calculating Fixed-MTRR Mask
Introduce the 32bit mask seeds to calculate Fixed-MTRR or&and mask values. It
could avoid the loop operation and 64bit shift operations.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29 10:07:07 +08:00
Jeff Fan aaa1e579a5 UefiCpuPkg/MtrrLib: Remove the loop of calculating byte offset in MSR
Calculate byte offset in MSR directly and removing the loop.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29 10:07:06 +08:00
Jeff Fan 0f35412232 UefiCpuPkg/MtrrLib: Reduce the loop time to get fixed-MTRR MSR index
Add input fixed-MTRR MSR index to be start MSR index to avoid finding fixed-MTRR
MSR index from 0 at each time.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29 10:07:06 +08:00
Laszlo Ersek fb8b54694c UefiCpuPkg: CpuIo2Dxe: optimize FIFO reads and writes of IO ports
* Short description:

  The CpuIoServiceRead() and CpuIoServiceWrite() functions transfer data
  between memory and IO ports with individual Io(Read|Write)(8|16|32)
  function calls, each in an appropriately set up loop.

  On the Ia32 and X64 platforms however, FIFO reads and writes can be
  optimized, by coding them in assembly, and delegating the loop to the
  CPU, with the REP prefix.

  On KVM virtualization hosts, this difference has a huge performance
  impact: if the loop is open-coded, then the virtual machine traps to the
  hypervisor on every single UINT8 / UINT16 / UINT32 transfer, whereas
  with the REP prefix, KVM can transfer up to a page of data per VM trap.
  This is especially noticeable with IDE PIO transfers, where all the data
  are squeezed through IO ports.

* Long description:

  The RootBridgeIoIoRW() function in

    PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c

  used to have the exact same IO port acces optimization, dating back
  verbatim to commit 1fd376d9792:

    PcAtChipsetPkg/PciHostBridgeDxe: Improve KVM FIFO I/O read/write
      performance

  OvmfPkg cloned the "PcAtChipsetPkg/PciHostBridgeDxe" driver (for
  unrelated reasons), and inherited the optimization from PcAtChipsetPkg.

  The "PcAtChipsetPkg/PciHostBridgeDxe" driver was ultimately removed in
  commit 111d79db47:

    PcAtChipsetPkg/PciHostBridge: Remove PciHostBridge driver

  and OvmfPkg too was rebased to the new core Pci Host Bridge Driver, in
  commit 4014885ffd:

    OvmfPkg: switch to MdeModulePkg/Bus/Pci/PciHostBridgeDxe

  This caused the optimization to go lost. Namely, the
  RootBridgeIoIoRead() and RootBridgeIoIoWrite() functions in the new core
  Pci Host Bridge Driver delegate IO port accesses to
  EFI_CPU_IO2_PROTOCOL. And, in OvmfPkg (and likely most other Ia32 / X64
  edk2 platforms), this protocol is provided by "UefiCpuPkg/CpuIo2Dxe",
  which lacks the optimization.

  Therefore, this patch ports the C source code logic from commit
  1fd376d979 (see above) to "UefiCpuPkg/CpuIo2Dxe", plus it ports the
  NASM-converted assembly helper functions from OvmfPkg commits
  6026bf4600 and ace1d0517b65:

    OvmfPkg PciHostBridgeDxe: Convert Ia32/IoFifo.asm to NASM

    OvmfPkg PciHostBridgeDxe: Convert X64/IoFifo.asm to NASM

  In order to support the MSFT and INTEL toolchains as well, the *.asm
  files are ported from OvmfPkg as well, immediately from before the above
  conversion (that is, at 6026bf460037^).

* Notes about the port:

  - The write and read branches from commit 1fd376d979 are split to the
    separate functions CpuIoServiceWrite() and CpuIoServiceRead().

  - The EfiPciWidthUintXX constants are replaced with EfiCpuIoWidthUintXX.

  - The cast expression "(UINTN) Address" is replaced with
    "(UINTN)Address" (i.e., no space), because that's how the receiving
    functions spell it as well.

  - The labels in the switch statements are unindented by one level, to
    match the edk2 coding style (and the rest of UefiCpuPkg) better.

* The first signoff belongs to Jordan, because he authored all of
  1fd376d979, 6026bf4600 and ace1d0517b.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Ref: https://www.redhat.com/archives/vfio-users/2016-April/msg00029.html
Reported-by: Mark <kram321@gmail.com>
Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/10424/focus=10432
Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Mark <kram321@gmail.com>
Tested-by: Mark <kram321@gmail.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-04-11 14:11:07 +02:00
Jeff Fan 4da1ebf3b3 UefiCpuPkg/CpuMpPei: Fix potential AP mwait wakeup issue
If ApLoopMode is set to ApInMwaitLoop, AP will be placed into C-State by mwait
instruction. BSP will wakeup AP by write start-up signal in monitor address.
However, AP maybe waken by SMI/NMI/MCE and other condition. On this case, AP
will check if BSP wants to wakeup itself really. If not, AP will continue to
execute mwait to C-State.

One potential issue: BSP may not recognize AP was wakeup from C-State by other
event and BSP still writes start-up signal to wakeup AP. But AP does not aware
it and still execute mwait instruction to C-State. So, AP cannot be wakeup on
this case.

This fix is let AP to clear start-up signal when it really is wakeup to execute
AP function. And BSP will write start-up signal till AP clears it.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-11 14:15:45 +08:00
Jeff Fan f5a2d6f012 UefiCpuPkg/Cpuid.h: Display Intel SGX Resource Enumeration Leaves
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-30 08:29:56 +08:00
Jeff Fan c606a9a5b7 UefiCpuPkg/Cpuid.h: Add CPUID defines and structures for Intel SGX
Add Intel SGX Resource Enumeration Leaves as described by Section 37.7 in
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D,
December 2015.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-30 08:29:49 +08:00
Laszlo Ersek 6c7f3f1d59 UefiCpuPkg: CpuMpPei: remove set but unused variables
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25 10:53:00 +01:00
Laszlo Ersek dc0a714314 UefiCpuPkg: PiSmmCpuDxeSmm: remove set but unused variables
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25 10:52:59 +01:00
Ard Biesheuvel 16e93125b5 UefiCpuPkg/MtrrLib: remove unused but set variable
Remove variable TempQWord that is declared, assigned but never referenced.
This fixes a warning emitted by GCC when -Wunused-but-set-variable is in
effect.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25 10:52:54 +01:00
Michael Kinney 195c94360f UefiCpuPkg/Include: Add top level MSR include file
Add top level MSR include file that includes the Architecural MSR
include file and all family specific MSR files from the Msr
subdirectory

Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR).

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 12:00:36 -07:00
Michael Kinney a1e8e34d74 UefiCpuPkg/Include: Add Pentium MSR include file
Add Pentium MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-20.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 12:00:19 -07:00
Michael Kinney 8e6bff8875 UefiCpuPkg/Include: Add P6 MSR include file
Add P6 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-19.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 12:00:08 -07:00
Michael Kinney 83d4e58cb0 UefiCpuPkg/Include: Add Pentium M MSR include file
Add Pentium M MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-18.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:59:56 -07:00
Michael Kinney e0d87abe8f UefiCpuPkg/Include: Add Core Solo/Duo MSR include file
Add Core Solo/Duo MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-17.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:59:44 -07:00
Michael Kinney f4d9afde4c UefiCpuPkg/Include: Add Pentium 4 MSR include file
Add Pentium 4 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-16.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:59:32 -07:00
Michael Kinney 3adf631660 UefiCpuPkg/Include: Add Xeon Phi MSR include file
Add Xeon Phi MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-15.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:59:20 -07:00
Michael Kinney 6b55a245f1 UefiCpuPkg/Include: Add Skylake MSR include file
Add Skylake MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-14.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:59:09 -07:00
Michael Kinney 54307cea18 UefiCpuPkg/Include: Add Xeon Processor D MSR include file
Add Xeon Processor D MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-13.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:58:58 -07:00
Michael Kinney d57201c0a3 UefiCpuPkg/Include: Add Broadwell MSR include file
Add Broadwell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-12.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:58:47 -07:00
Michael Kinney c67b579cd6 UefiCpuPkg/Include: Add Haswell-E MSR include file
Add Haswell-E MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-11.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:58:35 -07:00
Michael Kinney 7ae88a6295 UefiCpuPkg/Include: Add Haswell MSR include file
Add Haswell MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-10.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:58:24 -07:00
Michael Kinney 84ada87c6b UefiCpuPkg/Include: Add Ivy Bridge MSR include file
Add Ivy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-9.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:58:13 -07:00
Michael Kinney dc5d621c60 UefiCpuPkg/Include: Add Sandy Bridge MSR include file
Add Sandy Bridge MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-8.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:58:01 -07:00
Michael Kinney ebb74e4a3c UefiCpuPkg/Include: Add Xeon E7 MSR include file
Add Xeon E7 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-7.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:57:40 -07:00
Michael Kinney c5d7b07abb UefiCpuPkg/Include: Add Xeon 5600 MSR include file
Add Xeon 5600 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-6.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:57:24 -07:00
Michael Kinney bd946618a0 UefiCpuPkg/Include: Add Nehalem MSR include file
Add Nehalem MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-5.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:57:09 -07:00
Michael Kinney 053a6ae991 UefiCpuPkg/Include: Add Silvermont MSR include file
Add Silvermont MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-4.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:56:57 -07:00
Michael Kinney a646000f9b UefiCpuPkg/Include: Add Atom MSR include file
Add Atom MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-3.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:56:44 -07:00
Michael Kinney 63f3a74dd9 UefiCpuPkg/Include: Add Core 2 MSR include file
Add Core 2 MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-2.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:56:18 -07:00
Michael Kinney 04c980a630 UefiCpuPkg/Include: Add Architectural MSR include file
Add Architectural MSRs from:
Intel(R) 64 and IA-32 Architectures Software Developer's
Manual, Volume 3, December 2015, Chapter 35
Model-Specific-Registers (MSR), Section 35-1.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13 11:55:03 -07:00
Jeff Fan 70849819c1 UefiCpuPkg/Application/Cpuid: Remove unnecessary code check
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code.
UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;

Cc: Qiu Shumin <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
UefiCpuPkg/Application/Cpuid: Remove unnecessary code check

gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code.
UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;

Cc: Qiu Shumin <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
UefiCpuPkg/Application/Cpuid: Remove unnecessary code check

gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code.
UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;

Cc: Qiu Shumin <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-10 09:33:17 +08:00
Jeff Fan 321ef72c92 UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunction
Add check for gMaximumBasicFunction in CpuidVersionInfo () back.

Cc: Qiu Shumin <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-10 09:22:54 +08:00
Jeff Fan b1e01bd4e6 UefiCpuPkg: Add dynamic type for PcdCpuMaxLogicalProcessorNumber
Currently, PcdCpuMaxLogicalProcessorNumber only supports fixed type. There are
some requests on this PCD to support dynamic type also. For example, platform
may dynamically set this PCD to actual processor count to save memory or improve
boot performance.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-03-04 11:12:36 +08:00
Jeff Fan 5a676df9cd UefiCpuPkg/Application/Cpuid: Change DisplayFamily/DisplayModel type
Change DisplayFamily/DisplayModel type to UINT32 to avoid different size in
bitwise operation.

Cc: Qiu Shumin <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03 09:11:01 +08:00
Jeff Fan 2bdc0de6a5 UefiCpuPkg/Application/Cpuid: Remove unnecessary code check
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare
code.
UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;

Cc: Qiu Shumin <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03 09:10:56 +08:00
Jeff Fan 15dbb39332 UefiCpuPkg/CpuMpPei: Load microcode if found newer revision
Current implementation only loads the latest revision if there is no microcode
loaded. Per IA32 User Manual, we should load the newer revision by comparing
the existing microcode loaded with the updating revision.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03 09:10:15 +08:00
Hao Wu d2ba6f41e2 UefiCpuPkg/Cpuid: Fix GCC build error
define PRINT_BIT_FIELD(Variable, FieldName) \
  Print (L"%5a%42a: %x\n", #Variable, #FieldName, \
  ##Variable.Bits.##FieldName);

The above definition in UefiCpuPkg/Application/Cpuid/Cpuid.c
will cause GCC build error.

Fix it with:

define PRINT_BIT_FIELD(Variable, FieldName) \
  Print (L"%5a%42a: %x\n", #Variable, #FieldName, \
  Variable.Bits.FieldName);

The '.' has its origin meaning as a member operator in the define
statement. Thus, the token-pasting operator '##' is not necessary here.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-02-27 16:10:58 +08:00
Michael Kinney 2570575276 UefiCpuPkg/Cpuid: Add UEFI CPUID application
Add UEFI application to UefiCpuPkg to display all supported CPUID
leafs and sub-leafs described by UefiCpuPkg/Include/Register/Cpuid.h
that is based on information from Intel(R) 64 and IA-32
Architectures Software Developer's Manual, Volume 2A, December
2015, CPUID instruction.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-02-24 20:36:51 -08:00
Michael Kinney 57d16ba1e7 UefiCpuPkg/Cpuid.h: Add CPUID leaf/sub-leaf defines and structures
Add CPUID leaf and sub-leaf indexes and structures as described by
Intel(R) 64 and IA-32 Architectures Software Developer's Manual,
Volume 2A, December 2015, CPUID instruction.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-02-24 20:36:46 -08:00
Michael Kinney e1695f8dcf UefiCpuPkg/PiSmmCpuDxeSmm: Enable/Restore XD in SMM
If XD is supported, then SMM enables it.  The non-SMM execution
environment can choose to enable or disable XD, so the state of
XD must be detected in each SMI and be enabled/restored.

Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-02-22 10:59:41 -08:00
Michael Kinney d691abec1b UefiCpuPkg/PiSmmCpuDxeSmm: Add EFIAPI to CheckFeatureSupported()
The function CheckFeatureSupported() is used as an EFI_AP_PROCEDURE
in the MP Services Protocol service StartAllAPs().  Any function
used as an EFI_AP_PROCEDURE must use EFIAPI calling convention.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-02-22 10:35:28 -08:00
Hao Wu a7bd6695c5 UefiCpuPkg: Add NOOPT target in UefiCpuPkg.dsc
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19681 6f19259b-4bc3-4df7-8a09-765794883524
2016-01-19 04:08:09 +00:00
Liming Gao 2dc41d450a UefiCpuPkg: Add the missing module uni for CpuS3DataDxe
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19510 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24 02:30:43 +00:00
Michael Kinney 6011381199 UefiCpuPkg/PiSmmCpuDxeSmm: Initialize gSmst fields on S3 resume
Update S3 resume path to initialize the fields of gSmst before
the gSmst fields are used to complete initialization in S3 resume.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19504 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24 00:14:00 +00:00
Michael Kinney e9b3a6c926 UefiCpuPkg/PiSmmCpuDxeSmm: Correct CPUID leaf used to detect SMM mode
Use Bit 29 of CPUID leaf CPUID_EXTENDED_CPU_SIG (0x80000001) to
determine the SMM save state mode.  The previous version of this
code used CPUID leaf CPUID_VERSION_INFO (0x00000001).

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19503 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24 00:13:54 +00:00
Michael Kinney 3eed6dda20 UefiCpuPkg/PiSmmCpuDxeSmm: Fix failure when PcdCpuSmmDebug is TRUE
If PcdCpuSmmDebug is set to TRUE, then the first time the function
CpuSmmDebugEntry () is called during the first normal SMI, the
registers DR6 or DR7 may be set to invalid values due to gSmst
not being fully initialized yet.  Instead, use gSmmCpuPrivate that
is fully initialized for the first SMI to look up CpuSaveState
for the currently executing CPU.

Cc: Jeff Fan <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19502 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24 00:13:47 +00:00
Jeff Fan f63430abd3 UefiCpuPkg/CpuMpPei: Remove un-used AsmCliHltLoop()
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19347 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:26:40 +00:00
Jeff Fan a09647f3fe UefiCpuPkg/CpuMpPei: Wake up APs by proper method
If ApLoopMode is ApInHltLoop, BSP will send INIT-SIPI-SIPI to wake up APs.
If ApLoopMode is ApInMwaitLoop or ApInRunLoop, BSP will write one semaphore to
wake up APs.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19346 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:26:03 +00:00
Jeff Fan c87e41b445 UefiCpuPkg/CpuMpPei: Place APs in proper loop mode after AP execution
After AP function is executed, we will place AP in proper loop mode. Because AP
maybe waken up by SMI or other reasons. We need to read signature in monitor
buffer to check if APs is waken up by BSP. If it is not waken up by BSP, we will
continue to place them into proper loop mode.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19345 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:25:32 +00:00
Jeff Fan e001e11f90 UefiCpuPkg/CpuMpPei: Prepare for monitor buffer
Get AP loop mode to prepare for the monitor buffer required for ApInMwaitLoop
and ApInRunLoop.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19344 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:25:02 +00:00
Jeff Fan 4de216c016 UefiCpuPkg/CpuMpPei: Add GetApLoopMode() to get AP loop mode
Add GetApLoopMode() that will get PCD PcdCpuApLoopMode firstly. If it is
ApInMwaitLoop, we will check if MONITOR/MWAIT feature supported by CPUID. If
MONITOR/MWAIT feature is not supported, force AP loop mode to ApInHltLoop.

GetApLoopMode() also return the largest line size required.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19343 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:24:27 +00:00
Jeff Fan 9d39ed931b UefiCpuPkg: Add PCD PcdCpuApTargetCstate
This new PCD is used to specify the AP C-state value by MWAIT instruction.

More deeper C-state means more longer latency time when APs exiting from MWAIT
state. Platforms need to balance the performance and power saving to find the
proper C-state for APs.

Also, some processor may not ready for the deepest C-state at the beginning.
Platform also could choose the proper chance to place AP into the deeper C-state
by set this PCD before hand-off to OS.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19342 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:23:53 +00:00
Jeff Fan 54a3e8c9f5 UefiCpuPkg: Add PCD PcdCpuApLoopMode
This new PCD is used to specify the AP loop mode during POST phase.

The value 1 means we will place AP in the Hlt-Loop state by HLT instruction.
BSP need to send INIT-SIPI-SIPI to wake up APs.

The value 2 means we will place AP in the deepest C-state by MWAIT instruction.
BSP need to modify the monitor buffer by MONITOR instruction to wake up APs.

The value 3 means we will place AP in the Run-loop state. APs are running.
BSP need to write one semaphore to wake up APs.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19341 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:23:27 +00:00
Jeff Fan d603b1151c UefiCpuPkg/CpuMpPei: Fix pack(1) issue on x64 arch
Packing alignment for MP_CPU_EXCHANGE_INFO should be 1. This should be typo when
check-in CpuMpPei driver. IA32 arch MP_CPU_EXCHANGE_INFO is luckly pack(1). It
leads CpuMpPei x64 version hung.

Contributed-under: TianoCore Contribution Agreement 1.0
Reported-by: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19340 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18 03:22:56 +00:00
Jordan Justen 5999b89e22 UefiCpuPkg: Convert all .uni files to utf-8
To convert these files I ran:

$ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15 04:59:14 +00:00
Jeff Fan 4754f80b81 UefiCpuPkg/UefiCpuPkg.uni: Fix one typo
'.' should be '_'.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Shumin Qiu <shumin.qiu@intel.com>


git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19226 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-11 08:06:38 +00:00
Jeff Fan 2d675c1c8c UefiCpuPkg/MtrrLib:Initialize local variables before use them
Cc: Shumin Qiu <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Shumin Qiu <shumin.qiu@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19183 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10 07:10:13 +00:00
Jeff Fan abef2c8547 UefiCpuPkg/UefiCpuPkg.uni: Add PcdCpuNumberOfReservedVariableMtrrs
Cc: Shumin Qiu <shumin.qiu@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Shumin Qiu <shumin.qiu@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19182 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10 07:09:45 +00:00
Jeff Fan 5ac96e3a28 UefiCpuPkg/CpuMpPei: Add missing point at function header
Cc: Qiu Shumin <shumin.qiu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19165 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 07:51:29 +00:00
Michael Kinney b970ed6829 UefiCpuPkg/MtrrLib: Add MtrrSetMemoryAttributeInMtrrSettings()
Add new API MtrrSetMemoryAttributeInMtrrSettings() in MtrrLib. Platform could
use this API to set MTRR setting into local MTRR settings buffer instead of
MTRRs. At last, platform could use MtrrSetAllMtrrs() to set the MTRR settings
into MTRRs totally. It could improve MTRRs programming performance obviously,
specially when platform is going to program a set of MTRRs.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19162 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:26:26 +00:00
Michael Kinney 16c2d37e9a UefiCpuPkg/MtrrLib: Add MtrrDebugPrintAllMtrrsWorker()
MtrrDebugPrintAllMtrrsWorker() provides the capability to dump the MTRR setting
from MTRRs or the input MTRR settings buffer.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19161 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:25:48 +00:00
Michael Kinney 5abd5ed4c4 UefiCpuPkg/MtrrLib: Add worker functions to access MTRRs or variable
Add worker functions that could access MTRRs or MTRR settings in input buffer.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19160 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:25:21 +00:00
Michael Kinney e518b80d80 UefiCpuPkg/MtrrLib: Print MTRR settings when set fixed/variable MTRRs
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19159 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:24:48 +00:00
Michael Kinney b0fa5d29d0 UefiCpuPkg/MtrrLib: Reduce hardware init when program variable MTRRs
When MtrrSetMemoryAttribute() programs variable MTRRs, it may disable/enable
cache and disable/enable MTRRs several times. This updating tries to do
operation in local variable and does the hardware initialization one time only.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19158 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:24:18 +00:00
Michael Kinney fa25cf38d9 UefiCpuPkg/MtrrLib: Reduce hardware init when program fixed MTRRs
When MtrrSetMemoryAttribute() programs fixed MTRRs, it may disable/enable cache
and disable/enable MTRRs several times. This updating tries to do operation in
local variable and does the hardware initialization one time only.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19157 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:23:44 +00:00
Michael Kinney d0baed7db5 UefiCpuPkg/MtrrLib: Add MtrrGetMemoryAttributeInVariableMtrrWorker ()
Add function to shadow the content of variable MTRRs into an internal array:
VariableMtrr. And used MtrrGetMemoryAttributeInVariableMtrrWorker() in other
functions.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19156 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:23:13 +00:00
Michael Kinney acf431e6f7 UefiCpuPkg/MtrrLib: Make use of worker functions to get MTRRs count
Try to make use of worker functions to get MTRRs count. It could avoid invoking
IsMtrrSupported() for many times.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19155 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:22:42 +00:00
Michael Kinney 85b7f65b39 UefiCpuPkg/MtrrLib: Adjust functions order
Only adjust functions order and there is no any real functionality impact.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19154 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:22:01 +00:00
Michael Kinney 31b3597ee2 UefiCpuPkg/MtrrLib: Add worker functions not invoke IsMtrrSupported()
Abstract some worker functions not to invoke IsMtrrSupported(). They could be
used by other functions to reduce the number of invoking times on
IsMtrrSupported().

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19153 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:21:24 +00:00
Michael Kinney 76b4cae357 UefiCpuPkg/MtrrLib: Fix some typo and clean up code format
Fixed some typo. Removed some trailing spaces and TAB key. Clean up code format.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19152 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:20:44 +00:00
Jeff Fan 46309b1101 UefiCpuPkg/MtrrLib: Add PCD PcdCpuNumberOfReservedVariableMtrrs
Current MtrrLib reserves 2 variable MTRRs for some legacy OS boot (CSM boots)
may require some MTRRs to be reserved for OS use. But UEFI OS boot will not use
MTRRs.

Per Scott's suggestion in
link: http://article.gmane.org/gmane.comp.bios.edk2.devel/4099
Add one PCD PcdCpuNumberOfReservedVariableMtrrs to specify the number of
variable MTRRs reserved for OS use. Setting its default value to 2 is for
back-compatibility.

Cc: Scott Duplichan <scott@notabs.org>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Suggested-by: Scott Duplichan <scott@notabs.org>
Reviewed-by: Feng Tian <feng.tian@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19151 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08 05:19:34 +00:00
Jeff Fan 69206a0664 UefiCpuPkg/CpuS3DataDxe: Add more detailed description on GUID in INF
Add the GUID gEfiEndOfDxeEventGroupGuid usage description in more details in
INF file.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19100 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-03 01:13:57 +00:00
Jeff Fan c972495ed0 UefiCpuPkg/CpuMpPei: Fix typo and add some comments
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19090 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02 00:44:05 +00:00
Jeff Fan f40a7de450 UefiCpuPkg/CpuMpPei: Save/Restore CRx/DRx register for APs waking up
PeiStartupAllAPs()/PeiStartupThisAP() will send INIT-SIPI-SIPI to wakeup APs to
execute AP function. However, some registers will be reset after APs received
INIT IPI. We need to restore some registers (For example, CRx/DRx) manually
after APs wakeup.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19089 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02 00:43:45 +00:00
Jeff Fan 22cfe73a12 UefiCpuPkg/CpuMpPei: Sync BSP's CRx to APs when initialization
Save BSP's volatile register and sync CRx register to APs when AP 1st wake up.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19088 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02 00:43:19 +00:00
Jeff Fan 10c6c206da UefiCpuPkg/CpuMpPei: Set AP state to CpuStateIdle after initialization
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19087 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02 00:42:59 +00:00
Jeff Fan ef1fdb8098 UefiCpuPkg/CpuMpPei: Add CPU_VOLATILE_REGISTERS & worker functions
Add CPU_VOLATILE_REGISTERS definitions for CRx and DRx required to be restored
after APs received INIT IPI.

Add worker functions SaveVolatileRegisters()/RestoreVolatileRegisters() used to
save/restore CRx and DRx. It also check if Debugging Extensions supported or
not.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19086 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02 00:42:40 +00:00
Jeff Fan 24930b5609 UefiCpuPkg/CpuMpPei: Exchange whole CPU data in SortApicId()
Current implementation only exchanges the APIC ID and BIST, this updating is to
exchange all CPU data.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@Intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19085 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-02 00:42:09 +00:00
Yao, Jiewen 53ba3fb8aa UefiCpuPkg/PiSmmCpu: Always set WP in CR0
So that we can use write-protection for code later.

It is REPOST.
It includes suggestion from Michael Kinney <michael.d.kinney@intel.com>:
- "For IA32 assembly, can we combine into a single OR instruction that
  sets both page enable and WP?"
- "For X64, does it make sense to use single OR instruction instead of 2
  BTS instructions as well?"

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Suggested-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19068 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-30 19:57:45 +00:00
Yao, Jiewen 881520ea67 UefiCpuPkg/PiSmmCpu: Always set RW+P bit for page table by default
So that we can use write-protection for code later.

This is REPOST.
It includes the bug fix from "Paolo Bonzini" <pbonzini@redhat.com>:

  Title: fix generation of 32-bit PAE page tables

  "Bits 1 and 2 are reserved in 32-bit PAE Page Directory Pointer Table
  Entries (PDPTEs); see Table 4-8 in the SDM.  With VMX extended page
  tables, the processor notices and fails the VM entry as soon as CR0.PG
  is set to 1."

And thanks "Laszlo Ersek" <lersek@redhat.com> to validate the fix.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Signed-off-by: "Paolo Bonzini" <pbonzini@redhat.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19067 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-30 19:57:40 +00:00
Yao, Jiewen 21c1719318 UefiCpuPkg/PiSmmCpu: Update function call for 2 new APIs.
All page table allocation will use AllocatePageTableMemory().
Add SmmCpuFeaturesCompleteSmmReadyToLock() to PerformRemainingTasks()
and PerformPreTasks().

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18981 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-27 13:48:12 +00:00
Yao, Jiewen b095a5403b UefiCpuPkg/PiSmmCpu: Add NULL func for 2 new APIs in SmmCpuFeaturesLib.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18980 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-27 13:48:08 +00:00
Yao, Jiewen e3840072cd UefiCpuPkg/PiSmmCpu: Add 2 APIs in SmmCpuFeaturesLib.
SmmCpuFeaturesCompleteSmmReadyToLock() is a hook point to
allow CPU specific code to do more registers setting after
the gEfiSmmReadyToLockProtocolGuid notification is completely
processed.

SmmCpuFeaturesAllocatePageTableMemory() is an API to allow
CPU to allocate a specific region for storing page tables.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Laszlo Ersek" <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18979 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-27 13:48:03 +00:00
Laszlo Ersek 118930fa28 Revert "Add 2 APIs in SmmCpuFeaturesLib."
This reverts SVN r18958 / git commit
9daa916dd1.

The patch series had been fully reviewed on edk2-devel, but it got
committed as a single squashed patch. Revert it for now.

Link: http://thread.gmane.org/gmane.comp.bios.edk2.devel/4951
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18978 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-27 12:00:32 +00:00
Laszlo Ersek fc8c919525 Revert "Always set WP in CR0."
This reverts SVN r18960 / git commit
8e496a7abc.

The patch series had been fully reviewed on edk2-devel, but it got
committed as a single squashed patch. Revert it for now.

Link: http://thread.gmane.org/gmane.comp.bios.edk2.devel/4951
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18977 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-27 12:00:26 +00:00
Yao, Jiewen 8e496a7abc Always set WP in CR0.
Always set RW+P bit for page table by default.

So that we can use write-protection for code later.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18960 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-26 07:01:08 +00:00
Yao, Jiewen 9daa916dd1 Add 2 APIs in SmmCpuFeaturesLib.
Add NULL func for 2 new APIs in SmmCpuFeaturesLib.

SmmCpuFeaturesCompleteSmmReadyToLock() is a hook point to allow
CPU specific code to do more registers setting after
the gEfiSmmReadyToLockProtocolGuid notification is completely processed.
Add SmmCpuFeaturesCompleteSmmReadyToLock() to PerformRemainingTasks() and PerformPreTasks().

SmmCpuFeaturesAllocatePageTableMemory() is an API to allow
CPU to allocate a specific region for storing page tables.
All page table allocation will use AllocatePageTableMemory().

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18958 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-26 04:12:53 +00:00
Yao, Jiewen ae82a30bee Allocate Tile size based on Page.
We had better separate code from data in tile in page level,
so that other program may use page level protection on that.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18957 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-26 03:56:33 +00:00
Michael Kinney bfec5efa56 UefiCpuPkg/CpuS3DataDxe: Add module to initialize ACPI_CPU_DATA for S3
This module initializes the ACPI_CPU_DATA structure and registers the
address of this structure in the PcdCpuS3DataAddress PCD.  This is a
generic/simple version of this module.  It does not provide a machine
check handler or CPU register initialization tables for ACPI S3 resume.
It also only supports the number of CPUs reported by the MP Services
Protocol, so this module does not support hot plug CPUs.  This module
can be copied into a CPU specific package and customized if these
additional features are required.

This patch series is in response to the OvmfPkg patch series from
Laszlo Ersek that enables SMM on OVMF.  The v4 version of the patch
series from Laszlo includes an OVMF specific CPU module to initialize
the ACPI_CPU_DATA structure.

This proposed patch series replaces the patches listed below.

[PATCH v4 27/41] OvmfPkg:
  add skeleton QuarkPort/CpuS3DataDxe

[PATCH v4 28/41] OvmfPkg:
  QuarkPort/CpuS3DataDxe: fill in ACPI_CPU_DATA.StartupVector

[PATCH v4 29/41] OvmfPkg:
  QuarkPort/CpuS3DataDxe: handle IDT, GDT and MCE in ACPI_CPU_DATA

[PATCH v4 30/41] OvmfPkg:
  QuarkPort/CpuS3DataDxe: handle StackAddress and StackSize

[PATCH v4 31/41] OvmfPkg:
  import CpuConfigLib header from Quark_EDKII_v1.1.0/IA32FamilyCpuBasePkg

[PATCH v4 32/41] OvmfPkg:
  QuarkPort/CpuS3DataDxe: fill in ACPI_CPU_DATA.NumberOfCpus

[PATCH v4 33/41] OvmfPkg:
  QuarkPort/CpuS3DataDxe: fill in ACPI_CPU_DATA.MtrrTable

[PATCH v4 34/41] OvmfPkg:
  QuarkPort/CpuS3DataDxe: handle register tables in ACPI_CPU_DATA

[PATCH v4 35/41] OvmfPkg:
  port CpuS3DataDxe to X64
  patch originally authored by Paolo Bonzini

[PATCH v4 36/41] OvmfPkg:
  build QuarkPort/CpuS3DataDxe for -D SMM_REQUIRE

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: "Yao, Jiewen" <jiewen.yao@intel.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18951 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 17:01:02 +00:00
Michael Kinney af381fda9b UefiCpuPkg/Include: Expand description of AcpiCpuData.h structures
Provide a more detailed description of each field of the
ACPI_CPU_DATA and CPU_REGISTER_TABLE structures.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: "Yao, Jiewen" <jiewen.yao@intel.com>
Cc: "Fan, Jeff" <jeff.fan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Laszlo Ersek <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18950 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 17:00:51 +00:00
Yao, Jiewen f45f2d4ad4 Move SmmDebug feature from ASM to C.
SmmDebug feature is implemented in ASM, which is not easy to maintain.
So we move it to C function.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18946 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 08:51:15 +00:00
Yao, Jiewen 9f419739d1 Move RestoreSmmConfigurationInS3 function to PerformPreTasks().
In this way, we can centralize the silicon configuration in
PerformRemainingTasks()/PerformPreTasks() function.
If there are more features need to be configured, they can put in
PerformRemainingTasks()/PerformPreTasks() only.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>
Reviewed-by: "Laszlo Ersek" <lersek@redhat.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18938 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 04:28:46 +00:00
Yao, Jiewen fe5f194943 Eliminate EFI_IMAGE_MACHINE_TYPE_SUPPORTED.
Move Gdt initialization from InitializeMpServiceData() to CPU Arch specific function.
We create SmmFuncsArch.c for hold CPU specific function, so that
EFI_IMAGE_MACHINE_TYPE_SUPPORTED(EFI_IMAGE_MACHINE_X64) can be removed.

For IA32 version, we always allocate new page for GDT entry, for easy maintenance.
For X64 version, we fixed TssBase in GDT entry to make sure TSS data is correct.
Remove TSS fixup for GDT in ASM file.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Fan, Jeff" <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18937 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 04:23:01 +00:00
Yao, Jiewen 20ab326972 Correct TSS segment.
TSS segment should use (SIZE - 1) as limit, and do not set G bit (highest bit of LimitHigh) because limit means byte count.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Fan, Jeff" <jeff.fan@intel.com>
Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18935 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 04:01:00 +00:00
Jeff Fan c7981a1184 UefiCpuPkg/CpuMpPei: Enable x2APIC mode on BSP/APs
If x2APIC flag is set, enable x2APIC mode on all APs and BSP. Before we wakeup
APs to enable x2APIC mode, we should wait all APs have finished initialization.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18934 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-25 02:47:59 +00:00